707
edits
Contended I/O: Difference between revisions
Jump to navigation
Jump to search
m
Split out +3 sentence
(Avoid confusion with Z80 HALT instruction, mention clock-stopping and {{overline|WAIT}} signal) |
m (Split out +3 sentence) |
||
| Line 1: | Line 1: | ||
When the [[Z80]] wishes to access an IO port, it places the port address on the address bus exactly as it does when accessing memory. On the 48K and 128K Spectrums, this causes delays to IO as the ULA pauses the processor by stopping its clock, even when the ULA's I/O port is not the one being accessed. On the +3 Spectrum, no contention occurs as the +3 ULA applies contention only when the Z80's {{overline|MREQ}} line is active, which it is not during an IO operation. Two effects can occur here: | When the [[Z80]] wishes to access an IO port, it places the port address on the address bus exactly as it does when accessing memory. On the 48K and 128K Spectrums, this causes delays to IO as the ULA pauses the processor by stopping its clock, even when the ULA's I/O port is not the one being accessed. | ||
On the +3 Spectrum, no contention occurs as the +3 ULA applies contention only when the Z80's {{overline|MREQ}} line is active, which it is not during an IO operation. Two effects can occur here: | |||
# If the port address has its low bit reset, the ULA pauses the processor to supply the result using the {{overline|WAIT}} signal. | # If the port address has its low bit reset, the ULA pauses the processor to supply the result using the {{overline|WAIT}} signal. | ||