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→Timing differences
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== Timing differences == | == Timing differences == | ||
It has been observed that on ULA-based machines, the timings may be one tstate later than normal. All timings given in this documnet are for "early timing"; for "late timing", simply add one to add tstate counts given. ASIC-based machines manufactured by Amstrad do exhibit this | It has been observed that on ULA-based machines, the timings may be one tstate later than normal. All timings given in this documnet are for "early timing"; for "late timing", simply add one to add tstate counts given. ASIC-based machines manufactured by Amstrad do not exhibit this behaviour. | ||
The physical reason for this difference is that as the ULA heats up, it drifts from "early timing" to "late timing" due to increased thermal resistance. A machine that has been left off for some time and just switched on will always exhibit "early timing". Some emulators have a "late timing" option to switch the ULA to a "hot" state. | The physical reason for this difference is that as the ULA heats up, it drifts from "early timing" to "late timing" due to increased thermal resistance. A machine that has been left off for some time and just switched on will always exhibit "early timing". Some emulators have a "late timing" option to switch the ULA to a "hot" state. | ||