updated Timing differences section
== Timing differences ==
It has been observed that on
some machines, the timings have been observed to be consistently one tstate later than on other machines. All timings given in this document are for "early timing" machines; for late timing machines, simply add one to add tstate counts given.
The physical reason for this difference is
not well understood; in some emulators , the option for changing this behaviour refers to Zilog or clone CPUs, but both behaviours have been seen with both genuine Zilog and clone CPUs.
== Instruction breakdown ==