Contended memory: Difference between revisions

Contended memory (view source)

122 bytes added , 25 October 2013

updated Timing differences section

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 == Timing differences ==
-It has been observed that on some machines, the timings have been observed to be consistently one tstate later than on other machines. All timings given in this document are for "early timing" machines; for late timing machines, simply add one to add tstate counts given.
+It has been observed that on ULA-based machines, the timings may be one tstate later than normal. All timings given in this documnet are for "early timing"; for "late timing", simply add one to add tstate counts given. ASIC-based machines manufactured by Amstrad do exhibit this drift.
-The physical reason for this difference is not well understood; in some emulators, the option for changing this behaviour refers to Zilog or clone CPUs, but both behaviours have been seen with both genuine Zilog and clone CPUs.
+The physical reason for this difference is that as the ULA heats up, it drifts from "early timing" to "late timing" due to increased thermal resistance. A machine that has been left off for some time and just switched on will always exhibit "early timing". Some emulators have a "late timing" option to switch the ULA to a "hot" state.
 == Instruction breakdown ==