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Contended memory

122 bytes added, 06:54, 25 October 2013
updated Timing differences section
== Timing differences ==
It has been observed that on some ULA-based machines, the timings have been observed to may be consistently one tstate later than on other machinesnormal. All timings given in this document documnet are for "early timing" machines; for "late timing machines", simply add one to add tstate counts given. ASIC-based machines manufactured by Amstrad do exhibit this drift.
The physical reason for this difference is not well understood; in that as the ULA heats up, it drifts from "early timing" to "late timing" due to increased thermal resistance. A machine that has been left off for some time and just switched on will always exhibit "early timing". Some emulators, have a "late timing" option to switch the option for changing this behaviour refers ULA to Zilog or clone CPUs, but both behaviours have been seen with both genuine Zilog and clone CPUsa "hot" state.
== Instruction breakdown ==
86
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