Multiface: Difference between revisions

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831 bytes added ,  7 February 2021
m
I've corrected and answered the mistakes originally in the MF128 pcb picture.
m (Use interwiki links)
m (I've corrected and answered the mistakes originally in the MF128 pcb picture.)
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[[File:Mf128pcb.png|800px|Multiface 128 PCB]]
[[File:Mf128pcb.png|800px|Multiface 128 PCB]]


we can found an error and several questionable things.
we can find an error and several questionable things. -Thank you for pointing these out, that PCB layout is actually mine and I made it a long time ago and I have not actually re-created the pcb so indeed a couple of errors were present, I've checked and corrected on both the pcb-images (which I shall upload) as well as the text below.
 
* A, (questionable) Stealth mode flip-flop (IC7) data input pin (2) not connected. It should be connected to +5V, e.g. to the adjacent 72LS32 (IC6) Vcc pin (14).
* A, (questionable) Stealth mode flip-flop (IC7) data input pin (2) not connected. It should be connected to +5V, e.g. to the adjacent 72LS32 (IC6) Vcc pin (14).
* B, (error) The circled track (horizontal red) is connect IC3 2nd (based on Texas Instruments [https://www.ti.com/lit/ds/symlink/sn74ls27.pdf 74LS27 datasheet]) gate's output (pin 9) with IC9 1st (based on [https://www.ti.com/lit/ds/symlink/sn74ls32.pdf 74LS32 datasheet]) gate's output (pin 3). This track could not be here.
''* should be connected to the pin on the opposite side of the same IC. So pin 2 to pin 13''
* B, (error) The circled track (horizontal red) is connect IC3 2nd (based on Texas Instruments 74LS27 datasheet) gate's output (pin 9) with IC9 1st (based on 74LS32 datasheet) gate's output (pin 3). This track could not be here.
''* Yes that was a mistake, that short bit of track should not be there.''
* C, (questionable) Unused via.
* C, (questionable) Unused via.
''* Copied verbatim from the actual hardware, but is indeed not necessary.''
* D. (questionable) Unused via pair.
* D. (questionable) Unused via pair.
* E, (questionable) IC9 1st (based on Texas Instruments [https://www.ti.com/lit/ds/symlink/sn74ls32.pdf 74LS32 datasheet]) gate's 1st input pin (1) is unconnected. It should be connected somewhere probably the nearby {{overline|WR}} track (via of 6264 SRAM's pin (26) above this pin). So this gate makes a {{overline|WR}} + A15 logical function.
''* Again copied verbatim from the actual hardware, but are indeed not necessary.''
* F, (questionable) IC9 3rd (based on Texas Instruments [https://www.ti.com/lit/ds/symlink/sn74ls32.pdf 74LS32 datasheet]) gate output (pin 8) not connected somewhere. The track ended with a lone via.
* E, (questionable) IC9 1st (based on Texas Instruments 74LS32 datasheet) gate's 1st input pin (1) is unconnected. It should be connected somewhere probably the nearby WR track (via of 6264 SRAM's pin (26) above this pin). So this gate makes a WR + A15 logical function.
''* It actually connects to pin 27 right above it.''
* F, (questionable) IC9 3rd (based on Texas Instruments 74LS32 datasheet) gate output (pin 8) not connected somewhere. The track ended with a lone via.
''* You cannot tell from this pcb, but this Multiface has a through port and this lone via connects with a wire to the A15 pin of the through port edge connector pcb. The actual A15 from the other side is not connected. Also pin 15 of the through connector pcb connects to the Multiface pcb via a 1N4004 diode. It connects to the hole that has the small bit of track leading nowhere.''
 


There are three address decoding logic:
There are three address decoding logic:
5

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