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There are three address decoding logic:
* IC1 ([http 74LS260] 2x 5-input NOR gates), IC2 ([http 74LS30] a 8 input-NAND gate), one gate (2nd) of IC3 ([http 74LS27] 3x 3-input NOR gates) and one gate (2nd) of IC9 ([http 74LS32] 4x 2-input OR gates) decode opcode fetch from #0066 or #0067 (A1-A15, {{overline|M1}}, {{overline|MERQ}} and {{overline|RD}}). This used to trigger the Multiface 8k ROM (and of course of 8k RAM) to page in after the RED BUTTON push initiates an [[Non Maskable Interrupt]] (pulls {{overline|NMI}} line).* One gate (1st) of IC3, one gate (1st) of IC5 and one gate (1st) of IC10 ([ 74LS00] 4x 2-input NAND gates) and two gate (2nd and 4th) of IC6 ([http 74LS32] 4x 2-input-OR gate) decode port I/O from/to '''xxxx xxxx  x011 x1xx''' address (A2, A4-A5, {{overline|IORQ}}, {{overline|RD}} and {{overline|WR}}).The aid of a gate (3) of IC6 and 2 gates (3rd and 4th) of IC5 (A7) it used to manage the RED BUTTON stealth and page in/out logic.* One gate (1st) of IC9 and one gate (2nd) of IC3 decode write to I/O port '''0xxx xxxx  xxxx xx0x''' (A1, A15 and {{overline|WR}}). This used to store (D3) the selected video page in the 2nd D flip-flop of IC7 ([http 74LS74] 2x D-type flip-flop). See: [[ZX Spectrum 128#Paging|ZX Spectrum 128 Paging]] 
=== Multiface 3 ===

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