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DRAMS

2,399 bytes added, 02:23, 16 October 2016
pinouts and minimal description of DRAM chips used in ZX Spectrum 16/48
== DRAMS ==
Dynamic Random Access Memories used in ZX Sopectrum machines.

===4116===
16Kx1 bit DRAM chip

8 of this IC make the lower 16k part of the ZX Spectrum16/48 RAM.

e.g. NEC D416C-2

Pinout:

<tt>
{|
| style="text-align:right;" |
(-5V) V<sub>EE</sub><br>
D<sub>IN</sub><br>
{{overline|WE}}<br>
{{overline|RAS}}<br>
A<sub>0</sub><br>
A<sub>2</sub><br>
A<sub>1</sub><br>
(+12V) V<sub>DD</sub>
| style="border: 1px solid black" |
1&nbsp;°&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;16<br>
2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;15<br>
3&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;14<br>
4&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;13<br>
5&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;12<br>
6&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;11<br>
7&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;10<br>
8&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;9
||
GND (0V)<br>
{{overline|CAS}}<br>
D<sub>OUT</sub><br>
A<sub>6</sub><br>
A<sub>3</sub><br>
A<sub>4</sub><br>
A<sub>5</sub><br>
V<sub>CC</sub> (+5V)<br>
|}
</tt>

===4532===
32Kx1 bit DRAM chip

The addressing logic uses 8 line (A<sub>0</sub> to A<sub>7</sub>) for row address (RAS) and 7 line (A<sub>0</sub> to A<sub>6</sub>) for column address (CAS). At CAS the A<sub>7</sub> line has to be fixed at logic 0 or 1 depending on chip type.

8 of this IC make the upper 32k part of the ZX Spectrum48 RAM.

e.g:
TI TMS4532-20NL3 or OKI M3732-L
TI TMS4532-20NL4 or OKI M3732-H

Pinout:

<tt>
{|
| style="text-align:right;" |
NC<br>
D<sub>IN</sub><br>
{{overline|WE}}<br>
{{overline|RAS}}<br>
A<sub>0</sub><br>
A<sub>2</sub><br>
A<sub>1</sub><br>
(+5V) V<sub>CC</sub>
| style="border: 1px solid black" |
1&nbsp;°&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;16<br>
2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;15<br>
3&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;14<br>
4&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;13<br>
5&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;12<br>
6&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;11<br>
7&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;10<br>
8&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;9
||
GND (0V)<br>
{{overline|CAS}}<br>
D<sub>OUT</sub><br>
A<sub>6</sub><br>
A<sub>3</sub><br>
A<sub>4</sub><br>
A<sub>5</sub><br>
A<sub>7</sub><br>
|}
</tt>

A<sub>7</sub> should set logical 0 at {{overline|CAS}} for TI TMS4532-20NL3 and OKI M3732-L chips, and logical 1 for TI TMS4532-20NL4 and OKI M3732-H chips.

The A<sub>7</sub> line is omitted for refresh address.
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