707
edits
T34VG1: Difference between revisions
Jump to navigation
Jump to search
Mention the T34VG2
(Rewrite link to Baltik article on SpeccyWiki) |
(Mention the T34VG2) |
||
| Line 1: | Line 1: | ||
The '''T34VG1''' ('''Т34ВГ1''' in Cyrillic) is a custom chip performing a similar role to that of the [[ZX Spectrum ULA]] within various Eastern European Spectrum clones, most notably the [[Didaktik M]]. It is also sometimes labelled as a '''КА1515ХМ1-216''' or as just ULA1. Note that in Latin script, КА1515ХМ1-216 is transliterated as ''KA1515HM1-216''. The chip is sometimes referred to as a БМК so BMK, which is the Russian for gate array or uncommitted logic array. | The '''T34VG1''' ('''Т34ВГ1''' in Cyrillic) is a custom chip performing a similar role to that of the [[ZX Spectrum ULA]] within various Eastern European Spectrum clones, most notably the [[Didaktik M]]. It is also sometimes labelled as a '''КА1515ХМ1-216''' or as just ULA1. Note that in Latin script, КА1515ХМ1-216 is transliterated as ''KA1515HM1-216''. The chip is sometimes referred to as a БМК so BMK, which is the Russian for gate array or uncommitted logic array. | ||
Systems using | The '''T34VG2''' ('''Т34ВГ2''') adds an integrated floppy drive controller. | ||
Systems using the T34VG1 are typically clocked at 4 MHz. The chip uses the same scheme as the Amstrad CPC for sharing memory bandwidth between the CPU and video display engine, in that it introduces wait T-states (Tw states) by means of the Z80's {{overline|WAIT}} pin, so that memory accesses are aligned to groups of four clock cycles, resulting in execution of between 3–4 million T-states per second depending on the instructions that are executed. Wait states are inserted for access to any memory address, and for access to the ULA port ("port 0xfe"). These wait states are inserted as needed even whilst the border is being drawn and during vertical retrace, so as to provide consistent CPU performance. This consistency is needed, for example, when executing the ROM's beeper and tape routines, as instruction fetches from ROM are also subject to wait states. | |||
As the pixel clock is twice the CPU clock at 8 MHz, rather than the ~7 MHz pixel clock of the Spectrum, the screen is narrow in appearance. | As the pixel clock is twice the CPU clock at 8 MHz, rather than the ~7 MHz pixel clock of the Spectrum, the screen is narrow in appearance. | ||