T34VG1: Difference between revisions

Systems using this chip are typically clocked at 4 MHz.  The chip uses the same scheme as the Amstrad CPC for sharing memory bandwidth between the CPU and video display engine, in that it introduces wait T-states (Tw states) by means of the Z80's {{overline|WAIT}} pin, so that memory accesses are aligned to groups of four clock cycles, resulting in execution of between 3–4 million T-states per second depending on the instructions that are executed.  Wait states are inserted for access to any memory to which both the T34VG1 and Z80 have access, and for access to the ULA port ("port 0xfe").  These wait states are inserted as needed even whilst the border is being drawn and during vertical retrace, so as to provide consistent CPU performance.  This consistency is needed, for example, when executing the ROM's beeper and tape routines, as instruction fetches from ROM are also subject to wait states.

AR0–AR7 are multiplexed DRAM address lines.  The {{overline|CE}} signal can be used to prevent contention of ROM, but in this case, DRAM data lines must be connected to the Z80 data bus through resistors, such that the Z80 can execute from ROM whilst the T34VG1 fetches graphics data from DRAM.  The same technique can most likely be used to provide the CPU with fast access to RAM outside of the range of 0x4000–0x5aff provided the RAM in this area is accessed using a separate data and address bus.

Data bus resistors may be required simply to provide electrical protection to the T34VG1, but details of this are not yet clear.

The T34VG1 is decodes writes to port 0x5f which it signals using {{overline|SSWR}} and reads from port 0x1f which it signals using {{overline|SSRD}}.  It is speculated that both of these may simply decode A5, looking for it to go low.