707
edits
Contended memory: Difference between revisions
Jump to navigation
Jump to search
m
Update section headings
(Add to categories) |
m (Update section headings) |
||
| Line 7: | Line 7: | ||
== Details == | == Details == | ||
=== 16K | === 16K and 48K === | ||
On the 48K machine, the memory from 0x4000 to 0x7fff is contended. If the contended memory is accessed 14335<ref>In this document, we label the first tstate which ''begins'' with /INT low as tstate 0; some other resources label this tstate as tstate 1, which means that all tstate counts will be one greater. Note that this is purely a notational difference, and is ''not'' the same as the effect observed in the [[#Timing differences|timing differences]] section, which is a actual difference in behaviour between different machines; when using the notation which labels the first /INT low tstate as tstate 1, the first contended memory cycle is at either 14336 or 14337 tstates.</ref> or 14336 tstates after an interrupt (see the [[#Timing differences|timing differences]] section below for information on the 14335/14336 issue), the Z80 will be delayed for 6 tstates. After 14336 tstates, the delay is 5 tstates. The pattern continues as follows: | On the 48K machine, the memory from 0x4000 to 0x7fff is contended. If the contended memory is accessed 14335<ref>In this document, we label the first tstate which ''begins'' with /INT low as tstate 0; some other resources label this tstate as tstate 1, which means that all tstate counts will be one greater. Note that this is purely a notational difference, and is ''not'' the same as the effect observed in the [[#Timing differences|timing differences]] section, which is a actual difference in behaviour between different machines; when using the notation which labels the first /INT low tstate as tstate 1, the first contended memory cycle is at either 14336 or 14337 tstates.</ref> or 14336 tstates after an interrupt (see the [[#Timing differences|timing differences]] section below for information on the 14335/14336 issue), the Z80 will be delayed for 6 tstates. After 14336 tstates, the delay is 5 tstates. The pattern continues as follows: | ||
| Line 66: | Line 66: | ||
This pattern (6,5,4,3,2,1,0,0) continues until 14463 tstates after interrupt, at which point there is no delay for 96 tstates while the border and horizontal refresh are drawn. The pattern starts again at 14559 tstates and continues for all 192 lines of screen data. After this, there is no delay until the end of the frame as the bottom border and vertical refresh happen, and no delay until 14335 tstates after the start of the next frame as the top border is drawn. | This pattern (6,5,4,3,2,1,0,0) continues until 14463 tstates after interrupt, at which point there is no delay for 96 tstates while the border and horizontal refresh are drawn. The pattern starts again at 14559 tstates and continues for all 192 lines of screen data. After this, there is no delay until the end of the frame as the bottom border and vertical refresh happen, and no delay until 14335 tstates after the start of the next frame as the top border is drawn. | ||
=== 128K | === 128K and grey +2 === | ||
On the 128K and Grey +2 Spectrums, memory pages 1, 3, 5 and 7 are contended. This means that RAM from 0x4000 to 0x7fff is always contended (as memory page 5 is always mapped in there) and RAM from 0xc000 to 0xffff can be contended if page 1, 3, 5 or 7 is paged in there. The 128K and +2 Spectrums also have a different timing pattern from the 48K machine due to their different line and frame lengths: the 6,5,4,3,2,1,0,0 pattern starts 14361 tstates after interrupt, and repeats every 228 tstates rather than 224. | On the 128K and Grey +2 Spectrums, memory pages 1, 3, 5 and 7 are contended. This means that RAM from 0x4000 to 0x7fff is always contended (as memory page 5 is always mapped in there) and RAM from 0xc000 to 0xffff can be contended if page 1, 3, 5 or 7 is paged in there. The 128K and +2 Spectrums also have a different timing pattern from the 48K machine due to their different line and frame lengths: the 6,5,4,3,2,1,0,0 pattern starts 14361 tstates after interrupt, and repeats every 228 tstates rather than 224. | ||
=== Black +2 (+2A/B) | === Black +2 (+2A/B) and +3 === | ||
The Amstrad ASIC in the black +2A/+2B and +3 differs more significantly in that it applies less contention than the 48K or 128K/Grey +2 ULAs. Specifically, it applies memory contention only if the MREQ line is active, whereas the 16K/48K ULA applies it under all circumstances. | The Amstrad ASIC in the black +2A/+2B and +3 differs more significantly in that it applies less contention than the 48K or 128K/Grey +2 ULAs. Specifically, it applies memory contention only if the MREQ line is active, whereas the 16K/48K ULA applies it under all circumstances. | ||