ZX Spectrum ULA: Difference between revisions

From Sinclair Wiki
Jump to navigation Jump to search
mNo edit summary
m (tag Snow Effect with copyedit)
Line 20: Line 20:
Weirdly, the ULA also applies contention to IO port reads/writes if A15 =0 and A14 =1.  ''(details should go here; IO contention is more complicated somehow)''
Weirdly, the ULA also applies contention to IO port reads/writes if A15 =0 and A14 =1.  ''(details should go here; IO contention is more complicated somehow)''
=== The Snow Effect ===
=== The Snow Effect ===
{{Copyedit}}
Contention is also indirectly responsible for the famous "Snow Effect", produced by setting the Z80's 'interrupt vector' (I) register to a value in the range 0x40-0x7F.  This interacts with the Z80's memory refresh cycle: in the 3rd and 4th T-states of the M1 (opcode fetch) cycle, the Z80 pulls the /MREQ and /RFSH lines low, and asserts the R register in the low byte of the address bus; this is for dynamic RAM refresh.  However, when doing this, it also asserts the I register on the high byte of the address bus.  If I is in the range 0x40-0x7f, this will look to the ULA like an access to contended RAM (because the ULA doesn't check the /RD, /WR or /RFSH lines, only the /MREQ).  However, the ULA will only halt the Z80 on the first T-state of any M-cycle.
Contention is also indirectly responsible for the famous "Snow Effect", produced by setting the Z80's 'interrupt vector' (I) register to a value in the range 0x40-0x7F.  This interacts with the Z80's memory refresh cycle: in the 3rd and 4th T-states of the M1 (opcode fetch) cycle, the Z80 pulls the /MREQ and /RFSH lines low, and asserts the R register in the low byte of the address bus; this is for dynamic RAM refresh.  However, when doing this, it also asserts the I register on the high byte of the address bus.  If I is in the range 0x40-0x7f, this will look to the ULA like an access to contended RAM (because the ULA doesn't check the /RD, /WR or /RFSH lines, only the /MREQ).  However, the ULA will only halt the Z80 on the first T-state of any M-cycle.



Revision as of 11:02, 3 June 2011

The ULA (Uncommitted Logic Array) is a chip which controls most of the interfaces between the Z80 CPU and peripheral functions. On a ZX Spectrum 16k/48k, it is a Ferranti 5C102, 5C112 or 6C001 (the '102 had a timing fault which necessitated an extra board called the "spider mod"; the 6C001 alters the timing of the colour burst signal to improve performance with certain TV sets. (This info from the Spectrum Service Manual; don't know how to do citations on this wiki)).

ULA Functions

The ULA is responsible for:

  • Generating the display (in conjunction with the UHF modulator)
  • Tape and audio I/O
  • Reading the keyboard

From Z80 code, the ULA functions are accessible on any even-numbered I/O port (as the ULA performs very partial port decoding), but conventionally port 0xFE is used.

(list of the port high bytes & their interpretations should go here)

(stuff about keyboard half-rows should go here)

Contention

The ULA has priority for reading from RAM, since it needs to be able to generate the display promptly. Thus if the Z80 attempts to read/write memory from the range 0x4000 to 0x7FFF (ie. A15 =0, A14 =1) while the display is being generated, the ULA will stop the Z80 (by bringing the /WAIT line low) until it has finished reading VRAM. This is known as "RAM contention" and the range 0x4000 to 0x7FFF is the "contended RAM". While the TV scan is within the display area, contention is applied for 6 T-states out of every 8.

IO Contention

Weirdly, the ULA also applies contention to IO port reads/writes if A15 =0 and A14 =1. (details should go here; IO contention is more complicated somehow)

The Snow Effect

  • This article or section may be in need of copyediting for readability. You can help!

Contention is also indirectly responsible for the famous "Snow Effect", produced by setting the Z80's 'interrupt vector' (I) register to a value in the range 0x40-0x7F. This interacts with the Z80's memory refresh cycle: in the 3rd and 4th T-states of the M1 (opcode fetch) cycle, the Z80 pulls the /MREQ and /RFSH lines low, and asserts the R register in the low byte of the address bus; this is for dynamic RAM refresh. However, when doing this, it also asserts the I register on the high byte of the address bus. If I is in the range 0x40-0x7f, this will look to the ULA like an access to contended RAM (because the ULA doesn't check the /RD, /WR or /RFSH lines, only the /MREQ). However, the ULA will only halt the Z80 on the first T-state of any M-cycle.

The result of this is that the ULA won't assert the address it wants on the address bus, but it will still try to read the byte from RAM. This means it reads from whatever address was present on the bus, and uses that as the data to put on the screen. The upshot of all this is that the screen becomes filled with 'noise', almost as though the screen RAM had become corrupted - but the effect can be undone; putting the I register back will cause the screen to return to normal.

(I think there's more to it than this, I think you have to be running a sequence of 1-cycle instructions or something? Should probably find an example snow program to include)

(Also when people are talking about the snow effect they always seem to mention Arkanoid; presumably it uses the snow effect at some point)