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ZX Spectrum ULA: Difference between revisions
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Weirdly, the ULA also applies contention to IO port reads/writes if A15 =0 and A14 =1. ''(details should go here; IO contention is more complicated somehow)'' | Weirdly, the ULA also applies contention to IO port reads/writes if A15 =0 and A14 =1. ''(details should go here; IO contention is more complicated somehow)'' | ||
=== The Snow Effect === | === The Snow Effect === | ||
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Contention is also indirectly responsible for the famous "Snow Effect", produced by setting the Z80's 'interrupt vector' (I) register to a value in the range 0x40-0x7F. This interacts with the Z80's memory refresh cycle: in the 3rd and 4th T-states of the M1 (opcode fetch) cycle, the Z80 pulls the /MREQ and /RFSH lines low, and asserts the R register in the low byte of the address bus; this is for dynamic RAM refresh. However, when doing this, it also asserts the I register on the high byte of the address bus. If I is in the range 0x40-0x7f, this will look to the ULA like an access to contended RAM (because the ULA doesn't check the /RD, /WR or /RFSH lines, only the /MREQ). However, the ULA will only halt the Z80 on the first T-state of any M-cycle. | Contention is also indirectly responsible for the famous "Snow Effect", produced by setting the Z80's 'interrupt vector' (I) register to a value in the range 0x40-0x7F. This interacts with the Z80's memory refresh cycle: in the 3rd and 4th T-states of the M1 (opcode fetch) cycle, the Z80 pulls the /MREQ and /RFSH lines low, and asserts the R register in the low byte of the address bus; this is for dynamic RAM refresh. However, when doing this, it also asserts the I register on the high byte of the address bus. If I is in the range 0x40-0x7f, this will look to the ULA like an access to contended RAM (because the ULA doesn't check the /RD, /WR or /RFSH lines, only the /MREQ). However, the ULA will only halt the Z80 on the first T-state of any M-cycle. | ||
