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ZX Spectrum SE: Difference between revisions
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[[Category:Hardware]] | [[Category:Hardware]] | ||
[[Category:Spectrum]] | [[Category:Spectrum]] | ||
The ZX Spectrum SE is a second generation Spectrum clone created by Andrew Owen and Jarek Adamski in the final year of the twentieth century. Although only a single prototype was created, it is supported by a number of emulators on various platforms. | [[Category:Clones]] | ||
The ZX Spectrum SE is a second generation [[Spectrum clone]] created by Andrew Owen and Jarek Adamski in the final year of the twentieth century. Although only a single prototype was created, it is supported by a number of [[emulators]] on various platforms. | |||
== Technical Specification == | == Technical Specification == | ||
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* RAM: 280K (64K EX, 64K DOCK, 144K HOME, 8K PRAM) | * RAM: 280K (64K EX, 64K DOCK, 144K HOME, 8K PRAM) | ||
* ROM: 64K (32K active, 32K passive) | * ROM: 64K (32K active, 32K passive) | ||
* Sound: AY-3-8192 (on +128 and TS2068 port addresses) | * Sound: [[AY-3-8192]] (on +128 and TS2068 port addresses) | ||
* Joystick: Kempston (with +5v and 2nd button connection) | * Joystick: [[Kempston Joystick Interface|Kempston]] (with +5v and 2nd button connection) | ||
== Memory == | == Memory == | ||
The SE combines the RAM paging systems of the Timex TS2068 with the ZX Spectrum 128 and then adds another 16K to that. This means it uses two different systems to access its full 272K of RAM. Jarek installed his 128 compatibility upgrade to take the RAM to 144K and then installed a 128K SRAM connected to the Timex memory management unit. | The SE combines the RAM paging systems of the [[Timex TS2068]] with the ZX Spectrum 128 and then adds another 16K to that. This means it uses two different systems to access its full 272K of RAM. Jarek installed his 128 compatibility upgrade to take the RAM to 144K and then installed a 128K SRAM connected to the Timex memory management unit. | ||
The Timex Horizontal MMU sees the RAM as three banks of memory; HOME, DOCK, and EX banks. | The Timex Horizontal MMU sees the RAM as three banks of memory; HOME, DOCK, and EX banks. | ||
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Memory is paged in 8K banks from either the DOCK or the EX bank, but these banks are mutually exclusive - you cannot page in a bank from both simultaneously. Bit 7 of port 0xff determines which bank to use (0=DOCK, 1=EX-ROM). Port 0xf4 determines which banks are to be paged in with each bit referring to the relevant bank (0-7 or 0'-7'). When memory is being paged, interrupts should be disabled and the stack should be in an area which is not going to change. | Memory is paged in 8K banks from either the DOCK or the EX bank, but these banks are mutually exclusive - you cannot page in a bank from both simultaneously. Bit 7 of port 0xff determines which bank to use (0=DOCK, 1=EX-ROM). Port 0xf4 determines which banks are to be paged in with each bit referring to the relevant bank (0-7 or 0'-7'). When memory is being paged, interrupts should be disabled and the stack should be in an area which is not going to change. | ||
On a TC2048, BASIC is contained in the 16K ROM area and banks 0-7 and 0'-7' are not normally available, while on a TS2068 part of the BASIC is stored in an 8K ROM in bank 0' and cartridges plugged into the dock use banks 0-7. On the SE each of these banks is connected to 64K of RAM, providing an additional 128K in addition to the base RAM. | On a [[Timex TC2048|TC2048]], BASIC is contained in the 16K ROM area and banks 0-7 and 0'-7' are not normally available, while on a TS2068 part of the BASIC is stored in an 8K ROM in bank 0' and cartridges plugged into the dock use banks 0-7. On the SE each of these banks is connected to 64K of RAM, providing an additional 128K in addition to the base RAM. | ||
The contended memory timings for the SE are unknown but should be similar to that for the 48K machine, except that the pattern starts at a different number of T-states after the interrupt, than the usual 14335. Odd banks in the 128 scheme are contended. | The contended memory timings for the SE are unknown but should be similar to that for the 48K machine, except that the pattern starts at a different number of T-states after the interrupt, than the usual 14335. Odd banks in the 128 scheme are contended. | ||
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== Sound Chip == | == Sound Chip == | ||
The AY-3-8912 sound chip has an added 8K serial EEPROM. Port 14 of the AY is used as an IIC driver (must work as output). Bit 0 is the SDA (data) line, bit 1 is SCL (clock) of the IIC. The chip mapped to four I/O ports: | The [[AY-3-8912]] sound chip has an added 8K serial EEPROM. Port 14 of the AY is used as an IIC driver (must work as output). Bit 0 is the SDA (data) line, bit 1 is SCL (clock) of the IIC. The chip mapped to four I/O ports: | ||
OUT (0xfffd) - Select a register 0-14. | OUT (0xfffd) - Select a register 0-14. | ||
IN (0xfffd) - Read the value of the selected register. | IN (0xfffd) - Read the value of the selected register. | ||
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== SCLD == | == SCLD == | ||
The SE has a modified version of the TC2048 SCLD in place of the normal ULA. As a result the T-state timings are close to, but | The SE has a modified version of the TC2048 [[The Timex SCLD|SCLD]] in place of the normal [[The Spectrum ULA|ULA]]. As a result the T-state timings are close to, but subtly different from, the 48. | ||
The Spectrum's ULA bug which causes snow when I is set to point to contended memory is also present in the TC2048 SCLD (ULA) but has been fixed by Jarek by adding an AND gate. He has also fixed a problem with the SCLD which would produce snow if IM2 was selected. The TS2068 SCLD provides a number of additional screen modes controlled using port 0xff. An unfortunate side effect of this is that a few games, like Arkanoid, which expect reading 0xff to produce screen and ATTR data bytes when the ULA is reading screen memory, will not work because the value returned will be the last byte sent to the port. The SCLD is also responsible for I/O and unlike a normal Spectrum, port addresses are fully decoded. This means it is not possible to read the keyboard from alternate addresses which also causes problems with some games. Port 0xff is also used to enable/disable the timer interrupt and select which bank of memory should be used by the horizontal MMU. The byte to output will be interpreted thus: | The Spectrum's ULA bug which causes snow when I is set to point to contended memory is also present in the TC2048 SCLD (ULA) but has been fixed by Jarek by adding an AND gate. He has also fixed a problem with the SCLD which would produce snow if IM2 was selected. The TS2068 SCLD provides a number of additional screen modes controlled using port 0xff. An unfortunate side effect of this is that a few games, like Arkanoid, which expect reading 0xff to produce screen and ATTR data bytes when the ULA is reading screen memory, will not work because the value returned will be the last byte sent to the port. The SCLD is also responsible for I/O and unlike a normal Spectrum, port addresses are fully decoded. This means it is not possible to read the keyboard from alternate addresses which also causes problems with some games. Port 0xff is also used to enable/disable the timer interrupt and select which bank of memory should be used by the horizontal MMU. The byte to output will be interpreted thus: | ||
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* Timex Computer TC2068 | * Timex Computer TC2068 | ||
It can also emulate IF2 ROM cartridges and the Mikro-Plus cartridge. There is also a version of BBC Basic (Z80) available. | It can also emulate [[ZX Interface 2|IF2 ROM cartridges]] and the Mikro-Plus cartridge. There is also a version of BBC Basic (Z80) available. | ||
