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ZX Spectrum 16K/48K edge connector: Difference between revisions
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ZX Spectrum 16K/48K edge connector (view source)
Revision as of 23:45, 20 February 2012
, 20 February 2012IORQULA
m (us blank cell rather than "NC") |
(IORQULA) |
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|A3||12||12||D4 | |A3||12||12||D4 | ||
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|!IORQULA||13||13||!INT | |[[#IO Request Signals|!IORQULA]]||13||13||!INT | ||
|- | |- | ||
|0v||14||14||!NMI | |0v||14||14||!NMI | ||
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====CPU Clock==== | ====CPU Clock==== | ||
The !CK signal, sometimes referred to as PHICPU is available on Lower Pin 8. This clock signal is generated by the ULA and is interrupted during [[contended memory]] access. This clock signal is inverted by a transistor switch to provide a clean clock edge for the Z80. | The !CK signal, sometimes referred to as PHICPU is available on Lower Pin 8. This clock signal is generated by the ULA and is interrupted during [[contended memory]] access. This clock signal is inverted by a transistor switch to provide a clean clock edge for the Z80. | ||
====IO Request Signals==== | |||
The !IORQ signal generated by the Z80 is connected to the !IOREQ input of the ULA via a series resistor allowing the !IOREQ pin to be pulled high by TR6 when the A0 address line is high. This has the effect of allowing the ULA to respond to an IO request only when A0 is low. | |||
This combined !IORQ+A0 signal is connected to Lower Pin 13 and is referred to as !IORQULA or sometimes !IORQGE. | |||
Some peripherals use this as an input to inhibit the ULA !IOREQ even when A0 is low thereby allowing the use of even numbered ports. | |||
====Key Slot==== | ====Key Slot==== | ||
