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ZX Spectrum 16K/48K edge connector: Difference between revisions

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issue 6a !RFSH
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m (issue 6a !RFSH)
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[[Category:Spectrum]]
[[Category:Spectrum]]
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{{Template:Spectrum edge connector|A15|A13|D7|NC|[[#Key_Slot|SLOT]]|D0|D1|D2|D6|D5|D3|D4|{{overline|INT}}|{{overline|NMI}}|{{overline|HALT}}|{{overline|MREQ}}|{{overline|IORQ}}|{{overline|RD}}|{{overline|WR}}|[[#Power|-5v]]|{{overline|WAIT}}|[[#Power|+12v]]|[[#Power|12v AC]]|{{overline|M1}}|{{overline|RFSH}}|A8|A10|NC|A14|A12|[[#Power|+5v]]|[[#Power|+9v]]|[[#Key_Slot|SLOT]]|0v|0v|[[#CPU_Clock|{{overline|CK}}]]|A0|A1|A2|A3|[[#IO Request Signals|{{overline|IORQULA}}]]|0v|[[#Video_Outputs|VIDEO]]|[[#Video_Outputs|{{overline|Y}}]]|[[#Video_Outputs|V]]|[[#Video_Outputs|U]]|{{overline|BUSRQ}}|{{overline|RESET}}|A7|A6|A5|A4|{{overline|ROMCS}}|{{overline|BUSACK}}|A9|A11}}
{{Template:Spectrum edge connector|A15|A13|D7|NC|[[#Key_Slot|SLOT]]|D0|D1|D2|D6|D5|D3|D4|{{overline|INT}}|{{overline|NMI}}|{{overline|HALT}}|{{overline|MREQ}}|{{overline|IORQ}}|{{overline|RD}}|{{overline|WR}}|[[#Power|-5v]]|{{overline|WAIT}}|[[#Power|+12v]]|[[#Power|12v AC]]|{{overline|M1}}|[[#RFSH|{{overline|RFSH}}]]|A8|A10|NC|A14|A12|[[#Power|+5v]]|[[#Power|+9v]]|[[#Key_Slot|SLOT]]|0v|0v|[[#CPU_Clock|{{overline|CK}}]]|A0|A1|A2|A3|[[#IO Request Signals|{{overline|IORQULA}}]]|0v|[[#Video_Outputs|VIDEO]]|[[#Video_Outputs|{{overline|Y}}]]|[[#Video_Outputs|V]]|[[#Video_Outputs|U]]|{{overline|BUSRQ}}|{{overline|RESET}}|A7|A6|A5|A4|{{overline|ROMCS}}|{{overline|BUSACK}}|A9|A11}}
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====IO Request Signals====
====IO Request Signals====
The !IORQ signal generated by the Z80 is connected to the {{overline|IOREQ}} input of the [[The Spectrum ULA|ULA]] via a series resistor allowing the {{overline|IOREQ}} pin to be pulled high by TR6 when the A0 address line is high. This has the effect of allowing the ULA to respond to an IO request only when A0 is low.
The {{overline|IORQ}} signal generated by the Z80 is connected to the {{overline|IOREQ}} input of the [[The Spectrum ULA|ULA]] via a series resistor allowing the {{overline|IOREQ}} pin to be pulled high by TR6 when the A0 address line is high. This has the effect of allowing the ULA to respond to an IO request only when A0 is low.


This combined {{overline|IORQ}}+A0 signal is connected to Lower Pin 13 and is referred to as {{overline|IORQULA}} or sometimes {{overline|IORQGE}}.
This combined {{overline|IORQ}}+A0 signal is connected to Lower Pin 13 and is referred to as {{overline|IORQULA}} or sometimes {{overline|IORQGE}}.
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* Lower Pin 15 provides the same composite video signal that is fed into the UHF modulator.
* Lower Pin 15 provides the same composite video signal that is fed into the UHF modulator.
* Lower pin 16 carries an inverted luminosity signal to use with the 'U' and 'V' colour difference signals provided on lower pins 18 and 17 respectively. All three signals are generated by the [[The Spectrum ULA|ULA]].
* Lower pin 16 carries an inverted luminosity signal to use with the 'U' and 'V' colour difference signals provided on lower pins 18 and 17 respectively. All three signals are generated by the [[The Spectrum ULA|ULA]].
====RFSH====
The  {{overline|RFSH}} signal is '''not''' present on the ''issue 6A'' motherboard.