ZX Spectrum 16K/48K edge connector: Difference between revisions

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m (us blank cell rather than "NC")
(IORQULA)
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|A3||12||12||D4
|A3||12||12||D4
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|!IORQULA||13||13||!INT
|[[#IO Request Signals|!IORQULA]]||13||13||!INT
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|0v||14||14||!NMI
|0v||14||14||!NMI
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====CPU Clock====
====CPU Clock====
The !CK signal, sometimes referred to as PHICPU is available on Lower Pin 8. This clock signal is generated by the ULA and is interrupted during [[contended memory]] access. This clock signal is inverted by a transistor switch to provide a clean clock edge for the Z80.
The !CK signal, sometimes referred to as PHICPU is available on Lower Pin 8. This clock signal is generated by the ULA and is interrupted during [[contended memory]] access. This clock signal is inverted by a transistor switch to provide a clean clock edge for the Z80.
====IO Request Signals====
The !IORQ signal generated by the Z80 is connected to the !IOREQ input of the ULA via a series resistor allowing the !IOREQ pin to be pulled high by TR6 when the A0 address line is high. This has the effect of allowing the ULA to respond to an IO request only when A0 is low.
This combined !IORQ+A0 signal is connected to Lower Pin 13 and is referred to as !IORQULA or sometimes !IORQGE.
Some peripherals use this as an input to inhibit the ULA !IOREQ even when A0 is low thereby allowing the use of even numbered ports.


====Key Slot====
====Key Slot====

Revision as of 23:45, 20 February 2012

Lower Upper
A14 1 1 A15
A12 2 2 A13
+5v 3 3 D7
+9v 4 4
SLOT 5 5 SLOT
0v 6 6 D0
0v 7 7 D1
!CK 8 8 D2
A0 9 9 D6
A1 10 10 D5
A2 11 11 D3
A3 12 12 D4
!IORQULA 13 13 !INT
0v 14 14 !NMI
VIDEO 15 15 !HALT
!Y 16 16 !MREQ
V 17 17 !IORQ
U 18 18 !RD
!BUSRQ 19 19 !WR
!RESET 20 20 -5v
A7 21 21 !WAIT
A6 22 22 +12v
A5 23 23 12v AC
A4 24 24 !M1
!ROMCS 25 25 RFSH
BUSACK 26 26 A8
A9 27 27 A10
A11 28 28

The ZX Spectrum 16k/48k expansion connector is a double sided card edge connector with a 0.1 inch spacing. The two rows of conductors are numbered from right to left looking into the rear of the computer. One pair of conductors are missing as there is an indexing slot cut out of the circuit board.

Notes on Connections

CPU Clock

The !CK signal, sometimes referred to as PHICPU is available on Lower Pin 8. This clock signal is generated by the ULA and is interrupted during contended memory access. This clock signal is inverted by a transistor switch to provide a clean clock edge for the Z80.

IO Request Signals

The !IORQ signal generated by the Z80 is connected to the !IOREQ input of the ULA via a series resistor allowing the !IOREQ pin to be pulled high by TR6 when the A0 address line is high. This has the effect of allowing the ULA to respond to an IO request only when A0 is low. This combined !IORQ+A0 signal is connected to Lower Pin 13 and is referred to as !IORQULA or sometimes !IORQGE. Some peripherals use this as an input to inhibit the ULA !IOREQ even when A0 is low thereby allowing the use of even numbered ports.

Key Slot

The key slot ensures correct alignment of a peripheral with the edge connector. This slot is the width of one conductor and lies between Pin 4 and Pin 6, i.e. Pin 5 does not exist.

Power

  • Lower Pin 4 is connected to the +9 volt (nominal) DC supply from the ZX Spectrum PSU.
  • Lower Pin 3 is connected to the smoothed +5 volt DC output of the internal 7805 regulator.
  • Upper Pin 20 is connected to the -5 volt DC output of the internal power supply circuitry.
  • Upper Pin 22 is connected to the +12 volt DC output of the internal power supply circuitry.
  • Upper Pin 23 is connected to the oscillating voltage within the internal power supply circuitry. This is nominally 12 volts AC.
  • Lower Pins 6, 7, and 14 are connected to the 0 volt rail.

Video Outputs

Pin 15 on the lower side of the edge connector provides the same composite video signal that is fed into the UHF modulator. Lower pin 16 on the carries an inverted luminosity signal to use with the 'U' and 'V' colour difference signals provided on lower pins 18 and 17 respectively