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ZX Spectrum 128 edge connector: Difference between revisions

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[[Category:Spectrum]]
[[Category:Spectrum]]
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{{Template:Spectrum edge connector|A15|A13|D7|NC|[[#Key_Slot|SLOT]]|D0|D1|D2|D6|D5|D3|D4|!INT|!NMI|!HALT|!MREQ|!IORQ|!RD|!WR|[[#Power|-5v]]|!WAIT|[[#Power|+12v]]|[[#Power|12v AC]]|!M1|!RFSH|A8|A10|NC|A14|A12|[[#Power|+5v]]|[[#Power|+9v]]|[[#Key_Slot|SLOT]]|0v|0v|[[#CPU_Clock|!CK]]|A0|A1|A2|A3|[[#!IORQULA|NC]]|0v|[[#Removed Video Outputs|NC]]|[[#Removed Video Outputs|NC]]|[[#Removed Video Outputs|NC]]|[[#Removed Video Outputs|NC]]|!BUSRQ|!RESET|A7|A6|A5|A4|!ROMCS|!BUSACK|A9|A11}}
{{Template:Spectrum edge connector|A15|A13|D7|NC|[[#Key_Slot|SLOT]]|D0|D1|D2|D6|D5|D3|D4|{{overline|INT}}|{{overline|NMI}}|{{overline|HALT}}|{{overline|MREQ}}|{{overline|IORQ}}|{{overline|RD}}|{{overline|WR}}|[[#Power|-5v]]|{{overline|WAIT}}|[[#Power|+12v]]|[[#Power|12v AC]]|{{overline|M1}}|{{overline|RFSH}}|A8|A10|NC|A14|A12|[[#Power|+5v]]|[[#Power|+9v]]|[[#Key_Slot|SLOT]]|0v|0v|[[#CPU_Clock|{{overline|CK}}]]|A0|A1|A2|A3|[[#IORQULA|NC]]|0v|[[#Removed Video Outputs|NC]]|[[#Removed Video Outputs|NC]]|[[#Removed Video Outputs|NC]]|[[#Removed Video Outputs|NC]]|{{overline|BUSRQ}}|{{overline|RESET}}|A7|A6|A5|A4|{{overline|ROMCS}}|{{overline|BUSACK}}|A9|A11}}
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==The ZX Spectrum +2==
==The ZX Spectrum +2==
The [[ZX Spectrum +2]] uses the same pinout as the UK [[ZX Spectrum+ 128K|Spectrum+ 128K]] with the exception of Lower pin 13 which is connected to the [[#!IORQULA|!IORQGE]] input.
The [[ZX Spectrum +2]] uses the same pinout as the UK [[ZX Spectrum+ 128K|Spectrum+ 128K]] with the exception of Lower pin 13 which is connected to the [[#IORQULA|{{overline|IORQGE}}]] input.


==Notes on Connections==
==Notes on Connections==


====CPU Clock====
====CPU Clock====
The !CK signal, sometimes referred to as PHICPU is available on Lower Pin 8. This clock signal is generated by the [[The Spectrum ULA|ULA]] and is interrupted during [[contended memory]] access.
The {{overline|CK}} signal, sometimes referred to as PHICPU or &Phi;CPU is available on Lower Pin 8. This clock signal is generated by the [[The Spectrum ULA|ULA]] and is interrupted during [[contended memory]] access.


On the [[ZX Spectrum+ 128K|UK 128K]] the ULA clock pin is connected directly to the edge connector and is inverted by TR3 to drive the Z80.
On the [[ZX Spectrum+ 128K|UK 128K]] the ULA clock pin is connected directly to the edge connector and is inverted by TR3 to drive the Z80.


On the [[ZX Spectrum +2|+2]] the ULA clock pin is inverted by a NOT gate to generate the clock for the Z80. It is then inverted again by a second NOT gate to generate the edge connector !CK.
On the [[ZX Spectrum +2|+2]] the ULA clock pin is inverted by a NOT gate to generate the clock for the Z80. It is then inverted again by a second NOT gate to generate the edge connector {{overline|CK}}.


The !CK signal is '''NOT''' connected on the [[Investronica]] [[ZX Spectrum+ 128K]].
The {{overline|CK}} signal is '''NOT''' connected on the [[Investronica]] [[ZX Spectrum+ 128K]].


====!IORQULA====
===={{overline|IORQULA}}====
Some schematics label Lower Pin 13 as !IORQULA or !IORQGA, however this pin is '''NOT''' connected on either the [[Investronica]] or Sinclair [[ZX Spectrum+ 128K]]. It is connected on the [[ZX Spectrum +2]].
Some schematics label Lower Pin 13 as {{overline|IORQULA}} or {{overline|IORQGA}}, however this pin is '''NOT''' connected on either the [[Investronica]] or Sinclair [[ZX Spectrum+ 128K]]. It is connected on the [[ZX Spectrum +2]].


====Key Slot====
====Key Slot====
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====Removed Video Outputs====
====Removed Video Outputs====
Unlike the [[ZX Spectrum 16k/48k]] the [[ZX Spectrum+ 128K]] [[The Spectrum ULA|ULA]] generates RGB and Bright video signals rather than intensity and colour difference signals. The !Y, U, and V signals are therefore not available so the pins previously used for them are left unconnected. Additionally the composite video signal has been removed.
Unlike the [[ZX Spectrum 16k/48k]] the [[ZX Spectrum+ 128K]] [[The Spectrum ULA|ULA]] generates RGB and Bright video signals rather than intensity and colour difference signals. The {{overline|Y}}, U, and V signals are therefore not available so the pins previously used for them are left unconnected. Additionally the composite video signal has been removed.