ZX Spectrum 128: Difference between revisions

From Sinclair Wiki
Jump to navigation Jump to search
m (Fix link)
(Document 128K HAL faults)
Line 74: Line 74:
| || || Disable Paging || ROM Bank || Active Screen || colspan="3" | RAM Bank
| || || Disable Paging || ROM Bank || Active Screen || colspan="3" | RAM Bank
|}
|}
Due to a bug either in the 128K's HAL10H8 chip or in the 128K PCB, memory banks 1, 3, 5 and 7 are contended (and the rest uncontended) as opposed to 4, 5, 6 and 7 as documented in the service manual.  The +2 (with grey case) shares this fault, although it has been reported that later Spanish +2s were shipped with an updated HAL chip, which may have fixed this problem.
Reads from port 0x7ffd cause a crash, as the HAL does not distinguish these from writes, resulting in a floating data bus being used to set the paging registers.


==Keypad==
==Keypad==

Revision as of 23:21, 27 September 2015

  • This article is about the "toastrack" 128K model. For other Spectrum models with 128K of RAM see ZX Spectrum 128K models
Infobox: ZX Spectrum 128
Manufacturer Sinclair Research / Investrónica
Mfg. volume
CPU Z80A @ 3.5469MHz
ROM 32kB
RAM 128kB
as pages 8×16kB
Gfx Res 256×192
Gfx Colours 15 (2 per 8×8 cell)


Hardware

  • Processor: Zilog Z80A microprocessor clocked at 3.5469MHz.
  • ROM: 32KB ROM, arranged in 2 pages of 16KB.
  • RAM: 128KB of Dynamic RAM, arranged in 8 pages of 16KB.
  • Graphics: 256 × 192 pixels, 16 colours, attribute based. See Spectrum Video Modes.
  • Sound: AY-3-8912 3 channel, 8 octave Programmable Sound Generator and "beeper". Modulated onto video signal.
  • Keyboard: 58 plastic keys above a rubber pad and plastic membrane. Optional editor keypad.
  • I/O: Software controlled RS232 serial port. Keypad Port. Tape In (ear) and Tape Out (mic). Expansion I/O port.

Timings

Paging

The memory space of the Spectrum+ 128K is divided into four 16k pages. The 32k of ROM and 128k of RAM can be paged into the memory space as shown in the diagram below:

0xFFFF
-
0xC000
Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5
(screen 0)
Bank 6 Bank 7
(screen 1)
0xBFFF
-
0x8000
Bank 2
0x7FFF
-
0x4000
Bank 5
(screen 0)
0x3FFF
-
0x0000
ROM 0 ROM 1

Paging is controlled by performing I/O writes to ports 0x7ffd. The paging logic decodes the address bus partially (uses A15 and A1 lines only), so the exact port is 0xxx xxxx  xxxx xx0x.

The bits are described in the table below:

Port Bit
7 6 5 4 3 2 1 0
0x7ffd Disable Paging ROM Bank Active Screen RAM Bank

Due to a bug either in the 128K's HAL10H8 chip or in the 128K PCB, memory banks 1, 3, 5 and 7 are contended (and the rest uncontended) as opposed to 4, 5, 6 and 7 as documented in the service manual. The +2 (with grey case) shares this fault, although it has been reported that later Spanish +2s were shipped with an updated HAL chip, which may have fixed this problem.

Reads from port 0x7ffd cause a crash, as the HAL does not distinguish these from writes, resulting in a floating data bus being used to set the paging registers.

Keypad