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ZX Spectrum +2A/2B, +3/3B edge connector: Difference between revisions
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ZX Spectrum +2A/2B, +3/3B edge connector (view source)
Revision as of 23:49, 5 November 2012
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|[[#Power|+5v]]||3||3||D7 | |[[#Power|+5v]]||3||3||D7 | ||
|- | |- | ||
|NC||4||4||[[# | |NC||4||4||[[#ROM disable pins|NOE]] | ||
|- | |- | ||
|[[#Key_Slot|SLOT]]||5||5||[[#Key_Slot|SLOT]] | |[[#Key_Slot|SLOT]]||5||5||[[#Key_Slot|SLOT]] | ||
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|A3||12||12||D4 | |A3||12||12||D4 | ||
|- | |- | ||
|NC||13||13||NINT | |||
|- | |- | ||
|0v||14||14||NNMI | |0v||14||14||NNMI | ||
|- | |- | ||
|[[# | |[[#ROM disable pins|NOE]]||15||15||NHALT | ||
|- | |- | ||
|[[#Disc Controller Signals|NDRD]]||16||16||NMREQ | |[[#Disc Controller Signals|NDRD]]||16||16||NMREQ | ||
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|[[#Disc Controller Signals|NMTR]]||18||18||NRD | |[[#Disc Controller Signals|NMTR]]||18||18||NRD | ||
|- | |- | ||
|NBUSRQ||19||19|| | |NBUSRQ||19||19||NWR | ||
|- | |- | ||
|NRESET||20||20||NC | |NRESET||20||20||NC | ||
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|A4||24||24||NM1 | |A4||24||24||NM1 | ||
|- | |- | ||
|[[# | |[[#ROM disable pins|NC]]||25||25||NRFS | ||
|- | |- | ||
|NBUSACK||26||26||A8 | |NBUSACK||26||26||A8 | ||
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==Notes on Connections== | ==Notes on Connections== | ||
====CPU Clock==== | |||
The CKEXT signal is available on Lower Pin 8. The CPU clock signal is generated by the [[The Amstrad ASIC|ASIC]] (IC1) and is interrupted during [[contended memory]] access. This clock signal is fed into the Z80 via a series resistor. The CKEXT signal is inverted in relation to the CPU clock as it has been passed through a NOT gate. | |||
====Key Slot==== | |||
The key slot ensures correct alignment of a [[:category:peripherals|peripheral]] with the edge connector. This slot is the width of one conductor and lies between Pin 4 and Pin 6, i.e. Pin 5 does not exist. | |||
====Power==== | |||
The +2A/+3 and +2B are not powered from a single 9v supply as on all previous models, but by a multi rail supply. This provides the 5v, 12v, and -12v required directly and as such there is no 9v or -5v rail available on the edge connector for driving peripherals. | |||
====ROM disable pins==== | |||
All the previous models of ZX Spectrum have a single ROM chip which could be disabled to facilitate paging in external memory by pulling the !ROMCS line high. The +2A/+3 and +3B however have two ROM chips and brings them out to independent pins on the expansion port. The old !ROMCS pin (Lower pin 25) is not used, and instead Upper pin 4 and Lower pin 15 are used. These pins were both unused on the [[128k+|ZX Spectrum 128K Edge Connector]], however Lower pin 15 was used for composite video out on the [[16k/48k|ZX Spectrum 16k/48k Edge Connector]]. | |||
====Disc Controller Signals==== | |||
