651
edits
(3 intermediate revisions by the same user not shown) | |||
Line 8: | Line 8: | ||
====CPU Clock==== | ====CPU Clock==== | ||
The CKEXT signal is available on Lower Pin 8. The CPU clock signal is generated by the [[The Amstrad gate array|gate array]] (IC1) and is interrupted during [[contended memory]] access | The CKEXT signal is available on Lower Pin 8. The CPU clock signal is generated by the [[The Amstrad gate array|gate array]] (IC1) and is interrupted during [[contended memory]] access. The CKEXT signal is inverted in relation to the CPU clock input. | ||
====Key Slot==== | ====Key Slot==== | ||
Line 17: | Line 17: | ||
====ROM disable pins==== | ====ROM disable pins==== | ||
All the previous models of ZX Spectrum have a single ROM chip which could be disabled to facilitate paging in external memory by pulling the {{overline|ROMCS}} line high. The +2A/+3 and +3B however have two ROM chips and brings them out to independent pins on the expansion port. The old {{overline|ROMCS}} pin (Lower pin 25) is not used, and instead Upper pin 4 and Lower pin 15 are used. These pins were both unused on the [[ZX Spectrum 128K | All the previous models of ZX Spectrum have a single ROM chip which could be disabled to facilitate paging in external memory by pulling the {{overline|ROMCS}} line high. The +2A/+3 and +3B however have two ROM chips and brings them out to independent pins on the expansion port. The old {{overline|ROMCS}} pin (Lower pin 25) is not used, and instead Upper pin 4 and Lower pin 15 are used. These pins were both unused on the [[ZX Spectrum+ 128K edge connector|128K]], however Lower pin 15 was used for composite video out on the [[ZX Spectrum 16K/48K edge connector|16K/48K]]. | ||
====Disc Controller Signals==== | ====Disc Controller Signals==== |