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ZXI standard: Difference between revisions

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== Port Allocation ==
== Port Allocation ==
'''Port allocations are currently in flux - be advised that assignments may change in the future'''
To have your device certified as ZXI compliant, you must apply for the required number of I/O ports in the range #hh3B. This can be done by posting a request to usenet's comp.sys.sinclair, or to the [http://alistairsserver.no-ip.org/mailman/listinfo/zxi-specification-discussion zxi-specification-discussion mailing list]  
To have your device certified as ZXI compliant, you must apply for the required number of I/O ports in the range #hh3B. This can be done by posting a request to usenet's comp.sys.sinclair, or to the [http://alistairsserver.no-ip.org/mailman/listinfo/zxi-specification-discussion zxi-specification-discussion mailing list]  


The port ranges are assigned as follows
'''Allocations as of 05 September 2012'''
It is proposed that the 256 ZXI ports (#xx3B) be divided into two areas based on the state of the A15 line.
 
A plug-in ULA replacement (such as a ULAPlus implementation) fitted in place of the original ULA can only access the A14 and A15 lines of the high address byte. This means that only partial decoding is possible and the device will respond to 128 of the available 256 ports.


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A complete clone (i.e. not a plug-in ULA replacement) however can be given access to the full address bus and hence should decode the high bytes fully. It is proposed that any ports needed for internal functions in a clone (for example changing clock speed) be allocated from the higher 128 ports (i.e. A15 high).
#xF3B - ULAplus (see below)
#xE3B - ZX Prism
#xD3B - ZXI Hard Disk Interface Specification (working title)
#xC3B - Unassigned
#xB3B - Development/Testing. These ports should only be used during device development.
#xA3B - Unassigned
#x93B - Unassigned
#x83B - Unassigned
#x73B - Unassigned
#x63B - Unassigned
#x53B - Unassigned
#x43B - Unassigned
#x03B, #x13B, #x23B, and #x33B are to be used in groups where a device needs four ports (for example Spectranet which has the #0x3B assignments)
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Currently Allocated #x03B, #x13B, #x23B, and #x33B Ports
Current ZXI port assignments with A15 high:
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#033B - Spectranet page A memory select
#FF  : ULAplus data
#023B - Spectranet page B memory select
#C0-FE: Unassigned
#013B - Spectranet programmable trap register
#BF  : ULAplus register
#003B - Spectranet control register
#80-BE: Unassigned
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Currently used ULAplus ports
Current ZXI port assignments with A15 low:
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#FF3B - ULAplus data
#04-7F: Unassigned
#BF3B - ULAplus register
#03  : Spectranet page A memory select
#02  : Spectranet page B memory select
#01  : Spectranet programmable trap register
#00  : Spectranet control register
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