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ZX80/81 edge connector: Difference between revisions

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overline above prime
(Typographical changes)
m (overline above prime)
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[[Category:Hardware]]
[[Category:Hardware]]
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{{Template:ZX80/81 edge connector|[[#Data Bus|D7′]]|[[#Chip Select|{{overline|RAMCS}}]]|[[#Key Slot|SLOT]]|[[#Data Bus|D0′]]|[[#Data Bus|D1′]]|[[#Data Bus|D2′]]|[[#Data Bus|D6′]]|[[#Data Bus|D5′]]|[[#Data Bus|D3′]]|[[#Data Bus|D4′]]|{{overline|INT}}|{{overline|NMI}}|{{overline|HALT}}|{{overline|MREQ}}|{{overline|IORQ}}|{{overline|RD}}|{{overline|WR}}|{{overline|BUSAK}}|{{overline|WAIT}}|{{overline|BUSRQ}}|{{overline|RESET}}|{{overline|M1}}|{{overline|RFSH}}|[[#Power|+5{{small|V}}]]|[[#Power|+9{{small|V}}]]|[[#Key Slot|SLOT]]|0{{small|V}}|0{{small|V}}|[[#CPU Clock|{{overline|Φ}}]]|A0|A1|A2|A3|A15|A14|A13|A12|A11|A10|A9|A8|A7|A6|A5|A4|[[#Chip Select|{{overline|ROMCS′}}]]}}
{{Template:ZX80/81 edge connector|[[#Data Bus|D7′]]|[[#Chip Select|{{overline|RAMCS′}}]]|[[#Key Slot|SLOT]]|[[#Data Bus|D0′]]|[[#Data Bus|D1′]]|[[#Data Bus|D2′]]|[[#Data Bus|D6′]]|[[#Data Bus|D5′]]|[[#Data Bus|D3′]]|[[#Data Bus|D4′]]|{{overline|INT}}|{{overline|NMI}}|{{overline|HALT}}|{{overline|MREQ}}|{{overline|IORQ}}|{{overline|RD}}|{{overline|WR}}|{{overline|BUSAK}}|{{overline|WAIT}}|{{overline|BUSRQ}}|{{overline|RESET}}|{{overline|M1}}|{{overline|RFSH}}|[[#Power|+5{{small|V}}]]|[[#Power|+9{{small|V}}]]|[[#Key Slot|SLOT]]|0{{small|V}}|0{{small|V}}|[[#CPU Clock|{{overline|Φ}}]]|A0|A1|A2|A3|A15|A14|A13|A12|A11|A10|A9|A8|A7|A6|A5|A4|[[#Chip Select|{{overline|ROMCS′}}]]}}
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