Systems using this chip are typically clocked at 4 MHz. The chip uses the same scheme as the Amstrad CPC for sharing memory bandwidth between the CPU and video display engine, in that it introduces wait T-states (Tw states) by means of the Z80's WAIT pin, so that memory accesses are aligned to groups of four clock cycles, resulting in execution of between 3–4 million T-states per second depending on the instructions that are executed. Wait states are inserted regardless of the memory or I/O address being accessed, and are inserted even whilst the border is being drawn and during vertical retrace, so as to provide consistent CPU performance. This consistency is needed, for example, when executing the ROM's beeper and tape routines, as instruction fetches from ROM are also subject to wait states.
As the pixel clock is twice the CPU clock at 8 MHz, rather than the ~7 MHz pixel clock of the Spectrum, the screen is narrow in appearance.