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T34VG1: Difference between revisions
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Better document {{overline|SSRD}} and {{overline|SSWR}}
(→See also: Add link to speccy.info ULAs page) |
(Better document {{overline|SSRD}} and {{overline|SSWR}}) |
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AR0–AR7 are multiplexed DRAM address lines. Data bus resistors may be required simply to provide the T34VG1 with electrical protection from the Z80, but details of this are not yet clear. | AR0–AR7 are multiplexed DRAM address lines. Data bus resistors may be required simply to provide the T34VG1 with electrical protection from the Z80, but details of this are not yet clear. | ||
The T34VG1 is | The T34VG1 provides two pins for I/O port decoding. {{overline|SSRD}} has been confirmed to decode ports 0x7f, 0x3f, 0x5f, 0x6f, 0x77, 0x7b, 0x7d, but not ports 0xff or 0x7e. It can therefore be assumed that {{overline|SSRD}} is equal to {{overline|RD}} + {{overline|IORQ}} + A7 + {{overline|A0}}. {{overline|SSWR}} decodes port 0x5f (used for the paging of the ALF TV Game console), probably as {{overline|WR}} + {{overline|IORQ}} + A7 + {{overline|A0}}. | ||
The T34VG1 provides {{overline|CE}} as an output, which indicates whether an address within the ROM range (0x0000–0x3fff) is being accessed. | The T34VG1 provides {{overline|CE}} as an output, which indicates whether an address within the ROM range (0x0000–0x3fff) is being accessed. | ||
