User contributions for Cheveron
From Sinclair Wiki
30 September 2018
- 12:3112:31, 30 September 2018 diff hist +14 ZXI standard No edit summary
23 August 2018
- 09:2909:29, 23 August 2018 diff hist +93 Chloe 280SE No edit summary current
11 March 2015
- 16:2516:25, 11 March 2015 diff hist 0 ULAplus No edit summary
- 16:2216:22, 11 March 2015 diff hist −360 ULAplus No edit summary
5 August 2014
- 08:5508:55, 5 August 2014 diff hist +365 ULAplus No edit summary
- 08:5008:50, 5 August 2014 diff hist +11 ULAplus No edit summary
- 08:4908:49, 5 August 2014 diff hist −13 ULAplus No edit summary
- 08:4808:48, 5 August 2014 diff hist +118 ULAplus No edit summary
- 08:4208:42, 5 August 2014 diff hist +6 ULAplus No edit summary
- 08:4108:41, 5 August 2014 diff hist −111 ULAplus No edit summary
- 08:4108:41, 5 August 2014 diff hist +783 ULAplus v1.2. Port mirroring and planar modes.
4 August 2014
- 10:0610:06, 4 August 2014 diff hist +32 ULAplus →I/O ports
8 July 2014
- 14:3114:31, 8 July 2014 diff hist 0 ULAplus →Revision History
- 14:3114:31, 8 July 2014 diff hist −2 ULAplus No edit summary
- 14:3014:30, 8 July 2014 diff hist +1,045 ULAplus updated to revision 1.1
25 October 2013
- 06:5506:55, 25 October 2013 diff hist +8 Contended memory →Timing differences
- 06:5406:54, 25 October 2013 diff hist +122 Contended memory updated Timing differences section
27 September 2013
- 17:2117:21, 27 September 2013 diff hist +3 SE Basic IV No edit summary
22 September 2013
- 12:0812:08, 22 September 2013 diff hist +112 Chloe 140SE No edit summary
- 12:0612:06, 22 September 2013 diff hist +956 N Chloe 140SE Created page with "Category:Hardware Category:Spectrum Category:Clones category:timex {{Infobox computer | cpu = Z804C0020 @ 3.5MHz / 21MHz | rom = 32kB | ram = 128kB | ramp..."