Difference between revisions of "Multiface"
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Latest revision as of 10:06, 9 September 2018
The Multiface One/128/3 is a Multipurpose Interface created by Romantic Robot UK Ltd.
Schematic of multiface One
The Multiface 128 was released for the ZX Spectrum 128k models, including the original +2 model. It worked in 128K or 48K mode. The 128 introduced the ability to save to the +D and DISCiPLE disk systems, but lost its joystick port. The device was not compatible with the later Spectrum +2A or the Spectrum +3.
We haven't got a perfect schematic of Multiface 128. There is a PCB layout and a manual on WOS. The interface is build up 10 74LS TTL ICs, a 2764 8K EPROM and a 6264 8K static RAM. There are 4 D flip-flop (2x74LS74 IC4 and IC7) to manage RED BUTTON/NMI, stealth mode and store video memory page.
If we observe the PCB plan:
we can found an error and several questionable things.
- A, (questionable) Stealth mode flip-flop (IC7) data input pin (2) not connected. It should be connected to +5V, e.g. to the adjacent 72LS32 (IC6) Vcc pin (14).
- B, (error) The circled track (horizontal red) is connect IC3 2nd (based on Texas Instruments 74LS27 datasheet) gate's output (pin 9) with IC9 1st (based on 74LS32 datasheet) gate's output (pin 3). This track could not be here.
- C, (questionable) Unused via.
- D. (questionable) Unused via pair.
- E, (questionable) IC9 1st (based on Texas Instruments 74LS32 datasheet) gate's 1st input pin (1) is unconnected. It should be connected somewhere probably the nearby WR track (via of 6264 SRAM's pin (26) above this pin). So this gate makes a WR + A15 logical function.
- F, (questionable) IC9 3rd (based on Texas Instruments 74LS32 datasheet) gate output (pin 8) not connected somewhere. The track ended with a lone via.
There are three address decoding logic:
- IC1 (74LS260 2x 5-input NOR gates), IC2 (74LS30 a 8 input-NAND gate), one gate (2nd) of IC3 (74LS27 3x 3-input NOR gates) and one gate (2nd) of IC9 (74LS32 4x 2-input OR gates) decode opcode fetch from #0066 or #0067 (A1-A15, M1, MERQ and RD). This used to trigger the Multiface 8k ROM (and of course of 8k RAM) to page in after the RED BUTTON push initiates an Non Maskable Interrupt (pulls NMI line).
- One gate (1st) of IC3, one gate (1st) of IC5 and one gate (1st) of IC10 (74LS00 4x 2-input NAND gates) and two gate (2nd and 4th) of IC6 (74LS32 4x 2-input-OR gate) decode port I/O from/to xxxx xxxx x011 x1xx address (A2, A4-A5, IORQ, RD and WR).The aid of a gate (3) of IC6 and 2 gates (3rd and 4th) of IC5 (A7) it used to manage the RED BUTTON stealth and page in/out logic.
- One gate (1st) of IC9 and one gate (2nd) of IC3 decode write to I/O port 0xxx xxxx xxxx xx0x (A1, A15 and WR). This used to store (D3) the selected video page in the 2nd D flip-flop of IC7 (74LS74 2x D-type flip-flop). See: ZX Spectrum 128 Paging
The Multiface 3 was designed for ZX Spectrum +2A/2B, +3/3B models. The main feature of the Multiface 3 was its ability to save to +3 disk.