Multiface: Difference between revisions

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(IO → I/O as per Zilog Z80 and Spectrum BASIC manuals and Wikipedia)
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We haven't got a perfect schematic of Multiface 128. There is a [http://www.worldofspectrum.org/pub/sinclair/technical-docs/Multiface128_Schematics.zip PCB layout] and a [http://www.worldofspectrum.org/pub/sinclair/hardware-info/Multiface128_Manual.pdf manual] on WOS.
We haven't got a perfect schematic of Multiface 128. There is a [http://www.worldofspectrum.org/pub/sinclair/technical-docs/Multiface128_Schematics.zip PCB layout] and a [http://www.worldofspectrum.org/pub/sinclair/hardware-info/Multiface128_Manual.pdf manual] on WOS.
The interface is build up 10 [http://en.wikipedia.org/wiki/7400_series 74LS] [http://en.wikipedia.org/wiki/Transistor%E2%80%93transistor_logic TTL] ICs, a [[2764 EPROM|2764]] 8K EPROM and a [[6264 SRAM|6264]] 8K [http://en.wikipedia.org/wiki/Static_random-access_memory static RAM]. There are 4 D flip-flop (2x74LS74 IC4 and IC7) to manage RED BUTTON/NMI, sthealt mode and store video memory page.
The interface is build up 10 [http://en.wikipedia.org/wiki/7400_series 74LS] [http://en.wikipedia.org/wiki/Transistor%E2%80%93transistor_logic TTL] ICs, a [[2764 EPROM|2764]] 8K EPROM and a [[6264 SRAM|6264]] 8K [http://en.wikipedia.org/wiki/Static_random-access_memory static RAM]. There are 4 D flip-flop (2x74LS74 IC4 and IC7) to manage RED BUTTON/NMI, stealth mode and store video memory page.


If we observe the PCB plan:
If we observe the PCB plan:
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* IC1 ([http://www.futurlec.com/Datasheet/74ls/74LS260.pdf 74LS260] 2x 5-input NOR gates), IC2 ([http://www.ti.com/lit/ds/symlink/sn74ls30.pdf 74LS30] a 8 input-NAND gate), one gate (2nd) of IC3 ([http://www.ti.com/lit/ds/symlink/sn74ls27.pdf 74LS27] 3x 3-input NOR gates) and one gate (2nd) of IC9 ([http://www.ti.com/lit/ds/symlink/sn74ls32.pdf 74LS32] 4x 2-input OR gates) decode opcode fetch from #0066 or #0067 (A1-A15, {{overline|M1}}, {{overline|MERQ}} and {{overline|RD}}). This used to trigger the Multiface 8k ROM (and of course of 8k RAM) to page in after the RED BUTTON push initiates an [[Non Maskable Interrupt]] (pulls {{overline|NMI}} line).
* IC1 ([http://www.futurlec.com/Datasheet/74ls/74LS260.pdf 74LS260] 2x 5-input NOR gates), IC2 ([http://www.ti.com/lit/ds/symlink/sn74ls30.pdf 74LS30] a 8 input-NAND gate), one gate (2nd) of IC3 ([http://www.ti.com/lit/ds/symlink/sn74ls27.pdf 74LS27] 3x 3-input NOR gates) and one gate (2nd) of IC9 ([http://www.ti.com/lit/ds/symlink/sn74ls32.pdf 74LS32] 4x 2-input OR gates) decode opcode fetch from #0066 or #0067 (A1-A15, {{overline|M1}}, {{overline|MERQ}} and {{overline|RD}}). This used to trigger the Multiface 8k ROM (and of course of 8k RAM) to page in after the RED BUTTON push initiates an [[Non Maskable Interrupt]] (pulls {{overline|NMI}} line).
* One gate (1st) of IC3, one gate (1st) of IC5 and one gate (1st) of IC10 ([http://www.ti.com/lit/ds/symlink/sn74ls00.pdf 74LS00] 4x 2-input NAND gates) and two gate (2nd and 4th) of IC6 ([http://www.ti.com/lit/ds/symlink/sn74ls32.pdf 74LS32] 4x 2-input-OR gate) decode port I/O from/to '''xxxx xxxx  x011 x1xx''' address (A2, A4-A5, {{overline|IORQ}}, {{overline|RD}} and {{overline|WR}}).The aid of a gate (3) of IC6 and 2 gates (3rd and 4th) of IC5 (A7) it used to manage the RED BUTTON stealth and page in/out logic.
* One gate (1st) of IC3, one gate (1st) of IC5 and one gate (1st) of IC10 ([http://www.ti.com/lit/ds/symlink/sn74ls00.pdf 74LS00] 4x 2-input NAND gates) and two gate (2nd and 4th) of IC6 ([http://www.ti.com/lit/ds/symlink/sn74ls32.pdf 74LS32] 4x 2-input-OR gate) decode port I/O from/to '''xxxx xxxx  x011 x1xx''' address (A2, A4-A5, {{overline|IORQ}}, {{overline|RD}} and {{overline|WR}}).The aid of a gate (3) of IC6 and 2 gates (3rd and 4th) of IC5 (A7) it used to manage the RED BUTTON stealth and page in/out logic.
* One gate (1st) of IC9 and one gate (2nd) of IC3 decode write to I/O port '''0xxx xxxx  xxxx xx0x''' (A1, A15 and {{overline|WR}}). This used to store (D3) the selected video page in the 2nd D flip-flop of IC7 ([http://www.ti.com/lit/ds/symlink/sn74ls74a.pdf 74LS74] 2x D-type flip-flop). See: [[ZX_Spectrum%2B_128K#Paging|ZX Spectrum +128K Paging]]
* One gate (1st) of IC9 and one gate (2nd) of IC3 decode write to I/O port '''0xxx xxxx  xxxx xx0x''' (A1, A15 and {{overline|WR}}). This used to store (D3) the selected video page in the 2nd D flip-flop of IC7 ([http://www.ti.com/lit/ds/symlink/sn74ls74a.pdf 74LS74] 2x D-type flip-flop). See: [[ZX Spectrum 128#Paging|ZX Spectrum 128 Paging]]
=== Multiface 3 ===
=== Multiface 3 ===


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[[Category:Peripherals]]
[[Category:Peripherals]]
[[Category:Hardware]]
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