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(Multiface 128 technical details) |
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==== Technical details ==== | ==== Technical details ==== | ||
Schematic of multiface One [[File: | Schematic of multiface One [[File:Mf1sch.png|320px|Multiface One schematic]] | ||
=== Multiface 128 === | === Multiface 128 === | ||
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The interface is build up 10 [http://en.wikipedia.org/wiki/7400_series 74LS] [http://en.wikipedia.org/wiki/Transistor%E2%80%93transistor_logic TTL] ICs, a [[2764 EPROM|2764]] 8K EPROM and a [[6264 SRAM|6264]] 8K [http://en.wikipedia.org/wiki/Static_random-access_memory static RAM]. There are 4 D flip-flop (2x74LS74 IC4 and IC7) to manage RED BUTTON/NMI, sthealt mode and store video memory page. | The interface is build up 10 [http://en.wikipedia.org/wiki/7400_series 74LS] [http://en.wikipedia.org/wiki/Transistor%E2%80%93transistor_logic TTL] ICs, a [[2764 EPROM|2764]] 8K EPROM and a [[6264 SRAM|6264]] 8K [http://en.wikipedia.org/wiki/Static_random-access_memory static RAM]. There are 4 D flip-flop (2x74LS74 IC4 and IC7) to manage RED BUTTON/NMI, sthealt mode and store video memory page. | ||
If we observe the PCB plan [[File: | If we observe the PCB plan: | ||
[[File:Mf128pcb.png|800px|Multiface 128 PCB]] | |||
we can found an error and several questionable things. | |||
* A, (questionable) Stealth mode flip-flop (IC7) data input pin (2) not connected. It should be connected to +5V, e.g. to the adjacent 72LS32 (IC6) Vcc pin (14). | * A, (questionable) Stealth mode flip-flop (IC7) data input pin (2) not connected. It should be connected to +5V, e.g. to the adjacent 72LS32 (IC6) Vcc pin (14). | ||
* B, (error) The circled track (horizontal red) is connect IC3 2nd (based on Texas Instruments [http://www.ti.com/lit/ds/symlink/sn74ls27.pdf 74LS27 datasheet]) gate's output (pin 9) with IC9 1st (based on [http://www.ti.com/lit/ds/symlink/sn74ls32.pdf 74LS32 datasheet]) gate's output (pin 3). This track could not be here. | * B, (error) The circled track (horizontal red) is connect IC3 2nd (based on Texas Instruments [http://www.ti.com/lit/ds/symlink/sn74ls27.pdf 74LS27 datasheet]) gate's output (pin 9) with IC9 1st (based on [http://www.ti.com/lit/ds/symlink/sn74ls32.pdf 74LS32 datasheet]) gate's output (pin 3). This track could not be here. | ||
* C, (questionable) Unused via. | * C, (questionable) Unused via. | ||
* D. (questionable) Unused via pair. | * D. (questionable) Unused via pair. | ||
* E, (questionable) IC9 1st (based on Texas Instruments [http://www.ti.com/lit/ds/symlink/sn74ls32.pdf 74LS32 datasheet]) gate's 1st input pin (1) is unconnected. It should be connected somewhere probably the nearby {{overline|WR}} track ( | * E, (questionable) IC9 1st (based on Texas Instruments [http://www.ti.com/lit/ds/symlink/sn74ls32.pdf 74LS32 datasheet]) gate's 1st input pin (1) is unconnected. It should be connected somewhere probably the nearby {{overline|WR}} track (via of 6264 SRAM's pin (26) above this pin). So this gate makes a {{overline|WR}} + A15 logical function. | ||
* F, (questionable) IC9 3rd (based on Texas Instruments [http://www.ti.com/lit/ds/symlink/sn74ls32.pdf 74LS32 datasheet]) gate output (pin 8) not connected somewhere. The track ended with a lone via. | * F, (questionable) IC9 3rd (based on Texas Instruments [http://www.ti.com/lit/ds/symlink/sn74ls32.pdf 74LS32 datasheet]) gate output (pin 8) not connected somewhere. The track ended with a lone via. | ||
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[[Category:Peripherals]] | [[Category:Peripherals]] |
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