Floating bus: Difference between revisions
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When the Z80 reads from an unattached port it will read the data present on the ULA bus, which will be a display byte being transferred to the video circuits or 0xFF when idle, such as periods spent building the border. | When the Z80 reads from an unattached port it will read the data present on the ULA bus, which will be a display byte being transferred to the video circuits or 0xFF when idle, such as periods spent building the border. | ||
Each scanline of video memory fetches breaks down into a | Each scanline of video memory fetches breaks down into a 16×8 cycle sequence with two sets of display and attribute bytes (order: bitmap, attribute, bitmap+1, attribute+1) being fetched during the first 4 cycles followed by 4 idle cycles. The ULA bus remains idle for the remainder of each scanline and returns 0xFF. | ||
The following table shows the fetch cycles for the first 8 cycle sequence of the 48K and 128K models<ref>This document labels the first | The following table shows the fetch cycles for the first 8 cycle sequence of the 48K and 128K models<ref>This document labels the first T-state which ''begins'' with {{overline|INT}} low as T-state 0; some other resources label this as T-state 1 which will mean all T-state counts are one greater.</ref>: | ||
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! 48K | ! 48K | ||
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Note that these timings will all be one | Note that these timings will all be one T-state later on "[[Contended memory#Timing differences|late timing]]" machines. | ||
These [http://homepage.ntlworld.com/mark.woodmass/Float48k.tap 48K] and [http://homepage.ntlworld.com/mark.woodmass/Float128k.tap 128K] test programs may be used for testing an emulator's floating bus implementation. Note that the Z80 samples the data bus during the final T-state of the I/O machine cycle. All timings are relative to the ULA asserting the INTREQ line; as the Z80 samples this line during the final T-state of opcode execution, there is a minimum of a one cycle delay before the Z80 acknowledges the interrupt. | These [http://homepage.ntlworld.com/mark.woodmass/Float48k.tap 48K] and [http://homepage.ntlworld.com/mark.woodmass/Float128k.tap 128K] test programs may be used for testing an emulator's floating bus implementation. Note that the Z80 samples the data bus during the final T-state of the I/O machine cycle. All timings are relative to the ULA asserting the INTREQ line; as the Z80 samples this line during the final T-state of opcode execution, there is a minimum of a one cycle delay before the Z80 acknowledges the interrupt. | ||
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A number of commercial games used the floating bus effect, generally to synchronise with the display and allow for flicker-free drawing. Games known to use the floating bus include: | A number of commercial games used the floating bus effect, generally to synchronise with the display and allow for flicker-free drawing. Games known to use the floating bus include: | ||
* ''[[wikipedia:Arkanoid|Arkanoid]]'' (original release only, the Hit Squad | * ''[[wikipedia:Arkanoid|Arkanoid]]'' (original release only, the Hit Squad re-release does not use the floating bus) | ||
* ''[[wikipedia:Cobra (film)#Video game|Cobra]]'' (original release only, the Hit Squad | * ''[[wikipedia:Cobra (film)#Video game|Cobra]]'' (original release only, the Hit Squad re-release does not use the floating bus) | ||
* ''[[wikipedia:Sidewize|Sidewize]]'' | * ''[[wikipedia:Sidewize|Sidewize]]'' | ||
* [[wikipedia:Short_Circuit|Short Circuit]] | * [[wikipedia:Short_Circuit|Short Circuit]] | ||
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{{CC-BY-SA-techwiki|Floating bus|Floating_bus}} | {{CC-BY-SA-techwiki|Floating bus|Floating_bus}} | ||
[[Category:Hardware]] | |||
Revision as of 01:29, 23 May 2015
When the Z80 reads from an unattached port it will read the data present on the ULA bus, which will be a display byte being transferred to the video circuits or 0xFF when idle, such as periods spent building the border.
Each scanline of video memory fetches breaks down into a 16×8 cycle sequence with two sets of display and attribute bytes (order: bitmap, attribute, bitmap+1, attribute+1) being fetched during the first 4 cycles followed by 4 idle cycles. The ULA bus remains idle for the remainder of each scanline and returns 0xFF.
The following table shows the fetch cycles for the first 8 cycle sequence of the 48K and 128K models[1]:
| 48K | 128K | ULA bus |
|---|---|---|
| 14338 | 14364 | (0x4000) |
| 14339 | 14365 | (0x5800) |
| 14340 | 14366 | (0x4001) |
| 14341 | 14367 | (0x5801) |
| 14342 | 14368 | IDLE |
| 14343 | 14369 | IDLE |
| 14344 | 14370 | IDLE |
| 14345 | 14371 | IDLE |
Note that these timings will all be one T-state later on "late timing" machines.
These 48K and 128K test programs may be used for testing an emulator's floating bus implementation. Note that the Z80 samples the data bus during the final T-state of the I/O machine cycle. All timings are relative to the ULA asserting the INTREQ line; as the Z80 samples this line during the final T-state of opcode execution, there is a minimum of a one cycle delay before the Z80 acknowledges the interrupt.
The same effect is likely to be seen when reading unattached memory, such as reading the upper 32K on a 16K machine.
Commercial games
A number of commercial games used the floating bus effect, generally to synchronise with the display and allow for flicker-free drawing. Games known to use the floating bus include:
- Arkanoid (original release only, the Hit Squad re-release does not use the floating bus)
- Cobra (original release only, the Hit Squad re-release does not use the floating bus)
- Sidewize
- Short Circuit
Notes
- ↑ This document labels the first T-state which begins with INT low as T-state 0; some other resources label this as T-state 1 which will mean all T-state counts are one greater.
Article license information
This article uses material from the "Floating bus" article on the ZX Spectrum technical information wiki at Fandom (formerly Wikia) and is released under the Creative Commons Attribution-Share Alike License.