Contended memory: Difference between revisions

'''Contended memory''' is a quirk of the ZX Spectrum's hardware design which means that it is on average slower to access those memory areas which are shared with the ULA than it is to access other memory areas. This occurs because the RAM cannot be read by two devices (the ULA and the processor) at once, and the ULA is given higher priority so it can drawn the screen correctly. Therefore, programs which access this "contended memory" (which is from 0x4000 to 0x7fff on the 48K machine, which is the actual 16K version) or try to read from an I/O port where the result is provided by the ULA (any port with the low bit reset on the 48K machine) will be slowed if the ULA is reading the screen. This effect occurs only when the actual screen is being drawn; when the border is being drawn or the TV is in either horizontal or vertical refresh, the ULA does not need to access memory and therefore no delays occur.

On the 48K machine, the memory from 0x4000 to 0x7fff is contended. If the contended memory is accessed 14335<ref>In this document, we label the first tstate which ''begins'' with {{overline|INT}} low as tstate 0; some other resources label this tstate as tstate 1, which means that all tstate counts will be one greater. Note that this is purely a notational difference, and is ''not'' the same as the effect observed in the [[#Timing differences|timing differences]] section, which is a actual difference in behaviour between different machines; when using the notation which labels the first {{overline|INT}} low tstate as tstate 1, the first contended memory cycle is at either 14336 or 14337 tstates.</ref> or 14336 tstates after an interrupt (see the [[#Timing differences|timing differences]] section below for information on the 14335/14336 issue), the Z80 will be delayed for 6 tstates. After 14336 tstates, the delay is 5 tstates. The pattern continues as follows:

=== 128K and grey +2 ===

On the 128K and Grey +2 Spectrums, memory pages 1, 3, 5 and 7 are contended. This means that RAM from 0x4000 to 0x7fff is always contended (as memory page 5 is always mapped in there) and RAM from 0xc000 to 0xffff can be contended if page 1, 3, 5 or 7 is paged in there. The 128K and +2 Spectrums also have a different timing pattern from the 48K machine due to their different line and frame lengths: the 6,5,4,3,2,1,0,0 pattern starts 14361 tstates after interrupt, and repeats every 228 tstates rather than 224.

=== Black +2 (+2A/B) and +3 ===

The gate array in the black +2A/+2B and +3 differs more significantly in that it applies less contention than the 48K or 128K/Grey +2 ULAs. Specifically, it applies memory contention only if the MREQ line is active, whereas the 16K/48K ULA applies it under all circumstances.

Unlike the the 128K or Grey +2 the Amstrad gate array contends pages 4, 5, 6, and 7.

In the [[#Instruction breakdown|instruction breakdown table]], contention patterns which differ on the +2A/+3 are shown in '''bold''' in the '+3 ULA' column, with sections of 48K-specific contention shown in '''bold''' in the '48K/128K ULA' column.  T-state counts associated with the 48K-specific contention still apply to the +2A/+3 pattern, but the contention itself does not.  With 48K-contention excluded, the timings in both columns are identical.

The [[NTSC Spectrum]] has the same 6,5,4,3,2,1,0,0 contention pattern as the 48K machine, but starting at tstate 8959 rather than 14335.

It has been observed that on ULA-based machines, the timings may be one tstate later than normal. All timings given in this documnet are for "early timing"; for "late timing", simply add one to add T-state counts given. Machines based on the Amstrad gate array do not exhibit this behaviour.

In the table below, contention patterns which differ on the +2A/+3 are shown in '''bold''' in the '+3 ULA' column, with sections of 48K-specific contention shown in '''bold''' in the '48K/128K ULA' column.  T-state counts associated with the 48K-specific contention still apply to the +2A/+3 pattern, but the contention itself does not.  With 48K-contention excluded, the timings in both columns are identical.

! 48K/128 ULA

! +3 ULA