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Contended memory: Difference between revisions

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=== Black +2 (+2A/B) and +3 ===
=== Black +2 (+2A/B) and +3 ===


The Amstrad ASIC in the black +2A/+2B and +3 differs more significantly in that it applies less contention than the 48K or 128K/Grey +2 ULAs. Specifically, it applies memory contention only if the MREQ line is active, whereas the 16K/48K ULA applies it under all circumstances.
The gate arrau in the black +2A/+2B and +3 differs more significantly in that it applies less contention than the 48K or 128K/Grey +2 ULAs. Specifically, it applies memory contention only if the MREQ line is active, whereas the 16K/48K ULA applies it under all circumstances.
Unlike the the 128K or Grey +2 the Amstrad ASIC contends pages 4, 5, 6, and 7.
Unlike the the 128K or Grey +2 the Amstrad gate array contends pages 4, 5, 6, and 7.
In the [[#Instruction breakdown|instruction breakdown table]], contention patterns which differ on the +2A/+3 are shown in '''bold''' in the '+3 ULA' column, with sections of 48K-specific contention shown in '''bold''' in the '48K/128K ULA' column.  T-state counts associated with the 48K-specific contention still apply to the +2A/+3 pattern, but the contention itself does not.  With 48K-contention excluded, the timings in both columns are identical.
In the [[#Instruction breakdown|instruction breakdown table]], contention patterns which differ on the +2A/+3 are shown in '''bold''' in the '+3 ULA' column, with sections of 48K-specific contention shown in '''bold''' in the '48K/128K ULA' column.  T-state counts associated with the 48K-specific contention still apply to the +2A/+3 pattern, but the contention itself does not.  With 48K-contention excluded, the timings in both columns are identical.