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Contended memory: Difference between revisions
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The gate array in the +2A, +3, +2B, and +3B differs more significantly in that it applies less contention than the ULAs in the earlier models. Specifically, it applies memory contention only if the {{overline|MREQ}} line is active, whereas the 16K/48K ULA applies it under all circumstances. | The gate array in the +2A, +3, +2B, and +3B differs more significantly in that it applies less contention than the ULAs in the earlier models. Specifically, it applies memory contention only if the {{overline|MREQ}} line is active, whereas the 16K/48K ULA applies it under all circumstances. | ||
Unlike | Unlike the 128 or +2 the Amstrad gate array contends pages 4, 5, 6, and 7. | ||
In the [[#Instruction breakdown|instruction breakdown table]], contention patterns which differ on the gate array models are shown in '''bold''' in the 'Amstrad gate array' column, with sections of contention specific to the Ferranti ULAs shown in '''bold''' in the 'ULA' column. T-state counts associated with the ULA contention still apply to the gate array pattern, but the contention itself does not. With ULA contention excluded, the timings in both columns are identical. | In the [[#Instruction breakdown|instruction breakdown table]], contention patterns which differ on the gate array models are shown in '''bold''' in the 'Amstrad gate array' column, with sections of contention specific to the Ferranti ULAs shown in '''bold''' in the 'ULA' column. T-state counts associated with the ULA contention still apply to the gate array pattern, but the contention itself does not. With ULA contention excluded, the timings in both columns are identical. | ||
