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m (Zub moved page Contended IO to Contended I/O: IO → I/O as per Zilog Z80 and Spectrum BASIC manuals and Wikipedia) |
m (IO → I/O as per Zilog Z80 and Spectrum BASIC manuals and Wikipedia) |
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When the [[Z80]] wishes to access an | When the [[Z80]] wishes to access an I/O port, it places the port address on the address bus exactly as it does when accessing memory. On the 48K and 128K Spectrums, this causes delays to I/O as the ULA pauses the processor by stopping its clock, even when the ULA's I/O port is not the one being accessed. | ||
On the +3 Spectrum, no contention occurs as the +3 ULA applies contention only when the Z80's {{overline|MREQ}} line is active, which it is not during an | On the +3 Spectrum, no contention occurs as the +3 ULA applies contention only when the Z80's {{overline|MREQ}} line is active, which it is not during an I/O operation. [TODO: clarify whether port 0xfe can be accessed without delay.] | ||
On the 48K Spectrum and 128K Spectrum, two effects can occur here: | On the 48K Spectrum and 128K Spectrum, two effects can occur here: | ||
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The "Contention pattern" shows the sequence of (non-)contention which occurs: an entry of "N:x" means that the Z80 simply continues for x T states, while "C:x" means that the Z80 is paused for the same number of T states as with a normal [[contended memory]] access, before continuing for x T states. | The "Contention pattern" shows the sequence of (non-)contention which occurs: an entry of "N:x" means that the Z80 simply continues for x T states, while "C:x" means that the Z80 is paused for the same number of T states as with a normal [[contended memory]] access, before continuing for x T states. | ||
Access to ports between 0x4000 and 0x7ffe with the low bit clear (i.e. when the ULA's own port is not being accessed) is subject to contention on every T state, as neither the contention cancellation mechanism for memory requests nor the contention cancellation mechanism for ULA | Access to ports between 0x4000 and 0x7ffe with the low bit clear (i.e. when the ULA's own port is not being accessed) is subject to contention on every T state, as neither the contention cancellation mechanism for memory requests nor the contention cancellation mechanism for ULA I/O port access is triggered. Every T state of the I/O access is therefore treated as if it were the first T state of a memory access. | ||
== Notes == | == Notes == |