- This article is about the CPU chip used in the Spectrum. For the emulator snapshot format see Z80 format
The Zilog Z80A is the CPU used in the ZX80, ZX81 and all ZX Spectrum models, as well as most Spectrum clones and several other 8-bit micros. In the Spectrum, the Z80 is clocked at around 3.5MHz (for precise values see individual model pages).
- 1 Instruction set
- 2 Contended memory
- 3 Bits 3 and 5 of the F register
- 4 Differences between NMOS and CMOS Z80s
- 5 Bus
- 6 Replacements
- 7 Test programs
- 8 Notable uses
- 9 See also
- 10 External links
- 11 Article license information
- Main article: Z80 Programming#Instruction Set
The instruction set of the Z80 in an extension of that of the Intel 8080. An entirely different set of assembly mnemonics is used. 8080 compatibility allowed the Z80 to be used in many CP/M systems, and this compatibility allowed CP/M to run on the ZX Spectrum +3, and a CP/M compatible system, Pro-DOS, to run on the SAM Coupé.
Zilog have released a number of variants of the Z80, and it has been second-sourced by many manufacturers, such as Mostek. In addition, there are numerous processors such as the R800 and T80 that are largely compatible with the Z80's instruction set.
NEC produced an unlicensed clone of the Z80 (Computer History Museum: Z80 oral history page 13) through reverse engineering. It is this clone, the NEC µPD780 that is found in the majority of Spectrums, labelled as a "D780C -1".
The U880 was an East German clone of the Z80. This was also produced by Angstrem (Ангстрем) as the Т34ВМ1 in Cyrillic (T34VM1 in Latin script), which photomicrographs reveal to use the U880 die mask, and the КР1858ВМ1 in Cyrillic (KR1858VM1 in Latin script). These differ from the Zilog Z80 in their setting of the carry flag after an OUTI operation, but are otherwise (almost?) identical. The UB880D was found in the Didaktik Gama amongst other machines, despite being only rated for operation up to 2.5 MHz. The UA880D may run at 4 MHz. A CMOS clone, the КР1858ВМ3, also existed, and this is known to handle the HALT instruction differently: memory is not refreshed, R register is not incremented HALT during DI is permitted (but interrupts remain disabled afterwards) and HALT is interrupted immediately (rather after a delay, before the start of the next M-cycle).
- Main article: Contended memory
Computers using the Z80 tended to run at a relatively high clock speed by for the time, compared to certain other processors such as the MOS 6502 and Motorola 6809. Doing so was required to achieve a decent level of performance, as on average, the Z80 required a larger number of clock cycles per instruction executed. This high clock speed would typically eliminate cycle stealing as a means of sharing video memory between the display generation hardware and the CPU, as the DRAM required to support this would need to be clocked at an even higher frequency. If a display is to be generated whilst video memory is being accessed, this leaves a choice of comparatively expensive VRAM with a dedicated read port for display generation, or a memory contention scheme where by the CPU will is halted when the display hardware requires access to video memory.
The ZX Spectrum uses a memory contention scheme, but with a slight quirk — the MREQ line that signifies whether the Z80 is performing memory access is not decoded by the ULA of the original Sinclair models (including the 128K), meaning that the CPU may be halted briefly to avoid contention whenever it places a value onto the address bus in the address range of contended memory (i.e. memory at 0x4000–0x7fff on the 48K Spectrum, and also the range between 0xc000–0xffff on a 128K when contended memory is paged in). As MREQ is not decoded, this contention applies even when the Z80 is not accessing memory, i.e. when accessing I/O ports, when performing DRAM refresh, and when certain instructions place spurious values on the address bus for no specific purpose. This issue was later fixed by Amstrad for the Spectrum +3 and +2A/+2B, but by this time, a certain amount of software had grown to depend on the behaviour of the original Sinclair models.
Bits 3 and 5 of the F register
Upon executing BIT n,(HL) instructions, bits 3 and 5 of the F register are copied from an internally buffered register pair now commonly referred to as MEMPTR or WZ, as described in memptr_eng.txt.
Woody has confirmed that bits 3 and 5 of the flags are copied on all BIT instructions on both a Zilog Z80 and an NEC clone (stated on the link above as being "unverified").
Some bits which aren't immediately clear from memptr_eng.txt but appear to be generally true:
- MEMPTR is unchanged for DJNZ with B == 1 or for a conditional JR when the jump is not taken. (Note the difference with conditional JP and CALL where MEMPTR is set even if the jump isn't taken).
- MEMPTR is set for IN <register>, (C) and OUT (C), <register> for all registers, not just A.
- What is the value of MEMPTR after IN A, 255? Everywhere else that the high byte of MEMPTR is set to A, there is no carry from the low byte (eg LD (nnnn), A), but memptr_eng.txt implies there is a carry in this case. Has anyone checked this case?
SCF and CCF
Stuart Brady discovered that how bits 3 and 5 of the flags are set after the SCF and CCF instructions actually depends on the variant of Z80 in use. On a Zilog Z80, bits 3 and 5 of the flags were set by ORing their previous values with that of A. On an NEC clone, bit 3 was unaffected, while bit 5 appears to be set by ANDing the previous value with something unknown. Previously, Ian Greenway tested this and found that bits 3 and 5 seemed simply to be copied from A, although it is not known which CPU these tests were run on. For more details, see here, here and a more recent investigation here.
Patrik Rak however later discovered that the way how the flags 5 and 3 are affected after SCF/CCF actually depends on the previous instruction completed. In case of genuine Zilog CPU, if an instruction modifies the flags, the immediately following SCF/CCF does move of bits 5 and 3 from A to F, whereas if an instruction doesn't modify the flags (and after interrupt), the SCF/CCF does OR of bits 5 and 3 from A to F. In case of NEC and other clones, it is similar, except that instead of OR it does AND with some unknown value, making the result unreliable.
Differences between NMOS and CMOS Z80s
LD A,I and LD A,R bug
The NMOS Z80s suffer a problem whereby LD A,I and LD A,R record the state of IFF2 after it has been reset if an interrupt is delivered during that instruction. This behaviour, along with workarounds for this for use in interrupt handlers are documented in the Z80 Family Questions and Answers section of the Zilog Product Specifications Databook, and is useful for detecting the model of Z80 in use, so as to determine whether the CPU (assuming it is a genuine NMOS or CMOS Z80) provides an 'OUT (C),0' instruction (NMOS), or 'OUT (C),255' instead (CMOS).
OUT (C),0 or OUT (C),255 instruction
In 1996, Simon Cooke noted in a Usenet posting that the undocumented instruction usually referred to as 'OUT (C),0' behaves instead as 'OUT (C),255' on CMOS Z80s.
Later, in 2004, Colin Piggot rediscovered this with his own SAM Coupé, when running a demo for SCPDU 6, coincidentally written by Simon Cooke. With the CMOS Z80, a white background colour was set over part of the screen in the demo. This was described in SAM Revival Issue 9 (March/April 2004).
In 2008, this was once again rediscovered by the MSX community.
The Z80 has a 16-bit address bus and an 8-bit data bus. The control bus pins (all of which are active low) are:
|M1||Opcode Fetch Cycle|
|BUSRQ||Bus (DMA) request|
|BUSACK||Bus (DMA) acknowledgement|
All of these signals, including A0–A15 and D0–D7, are accessible on the expansion bus of both the ZX Spectrum and ZX81, although note that the ZX81's BUSACK signal is inverted, and that pinouts differ between the two machines.
Z80 chips are still available new, due largely to their continued popularity for embedded systems. Component suppliers such as Farnell and Rapid usually have them in stock.
A basic Flags test program for emulators is available here. Note that the program makes heavy use of ROM data during the tests and so should only be used with an unpatched copy of the original 48K ROM to obtain correct results.
The SAM Coupé, a computer with a large degree of compatibility with the ZX Spectrum 48K, makes use of a Z80B, running at 6 MHz.
The Sega Master System and Sega Game Gear use a Z80 as their CPU. The Nintendo Game Boy makes use of a Sharp LR35902, which is closer to an Intel 8080, but includes a number extra instructions from the Z80 (but not the extra registers) and some unique instructions of its own.
- X80, a proposed floating point unit following the Spectrum calculator stack instruction set.
- Wikipedia's article on the Z80
- Thomas Scherrer's z80.info: official Zilog manuals and the like
- Sean Young's The Undocumented Z80 Documented: undocumented features
- U880 (link to German language Wikipedia)
- Т34ВГ1 (link to Russian language Wikipedia)
- T34VM1 (link to Czech language Wikipedia)